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Iraj Living Tr Motabar

from Laguna Niguel, CA
Age ~56
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Also known as:
Iraj I Motabar, Iraj X Motabar, Zadeh Iraj Motabar, Iraj Motabar Zadeh, Iraj M Zadeh, Iraj Motabar Motabarzadeh, Irha Motabar
Phone and address:
4 Pembroke Ln, Laguna Beach, CA 92677
(949) 266-7379
Related to:
Sahar Motabar, 46Nosrat Ranjbaran, 65Mohammad M Ranjbaran, 67Iraj Motabarzadeh, 56Sahar Motabarzadeh, 46Sahahar Motabar
Connected to:
Lisa M Motacki, 36Rubin Motaev, 51Mohammad R Motaghi, 65Scott M Motaka, 47Amber Motal, 30Benjamin J Motal, 41Brooke A Motal, 35Mohamed A Motala, 91Mohammed Motaleb, 55Isaac P Motamarry, 46

Iraj Motabar Phones & Addresses

  • 4 Pembroke Ln, Laguna Niguel, CA 92677 (949) 266-7379
  • 8 Chinaberry, Irvine, CA 92618 (949) 387-0776
  • 451 Shadow Oaks, Irvine, CA 92618
  • 6221 Pimlico Rd, Baltimore, MD 21209 (410) 358-0757
  • 445 Coventry Trail Ln, Maryland Heights, MO 63043 (314) 739-1848 (314) 739-1894
  • Saint Louis, MO
  • Orange, CA
  • Capistrano Beach, CA
  • Maryland Hts, MO
  • 4 Pembroke Ln, Laguna Niguel, CA 92677

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

Iraj Motabar Photo 1

Associate Technical Director

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Location:
Orange, CA
Industry:
Semiconductors
Work:
Broadcom Nov 1, 2006 - May 1, 2011
Senior Principal Design Scientist
Broadcom Nov 1, 2006 - May 1, 2011
Associate Technical Director
Quartics Dec 1, 2005 - Nov 1, 2006
Principal Design Engineer
Erlang Technology Nov 1, 1999 - Dec 1, 2005
Director of Engineering
Education:
The Johns Hopkins University Aug 1998 - Nov 1999
Washington University In St. Louis Oct 1994 - 1998
Doctorates, Doctor of Philosophy, Biomedical Engineering Amirkabir University of Technology - Tehran Polytechnic 1991 - 1994
Masters, Master of Science In Electrical Engineering, Biomedical Engineering Iran University of Science and Technology Aug 1987 - 1991
Bachelors, Bachelor of Science In Electrical Engineering, Engineering Technical High School of the Iranian Oil Ministry Aug 1983 - 1987
Skills:
Asic
Ic
Verilog
Processors
Embedded Systems
Hardware Architecture
Soc
Semiconductors
Fpga
Software Development
Timing Closure
Logic Synthesis
Rtl Design
Integrated Circuit Design
Eda
Functional Verification
Static Timing Analysis
Vlsi
Systemverilog
Circuit Design
Simulations
Engineering
Networking
Mixed Signal
Microprocessors
Low Power Design
Signal Processing
Pll
Tcl
Iraj Motabar Photo 2

Iraj Motabar

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Iraj Motabar Photo 3

Iraj Motabar

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Position:
Sr. Principal Design Scientist at Broadcom - Office of CTO
Location:
Orange County, California Area
Industry:
Semiconductors
Work:
Broadcom - Office of CTO since May 2011
Sr. Principal Design Scientist
Broadcom - Broadband Communications Nov 2006 - May 2011
Sr. Principal Design Scientist
Quartics, Inc. Dec 2005 - Nov 2006
Principal Design Engineer
Erlang Technology, Inc. Nov 1999 - Dec 2005
Director of Engineering
Education:
The Johns Hopkins University Aug 1998 - Nov 1999
Washington University in St. Louis Oct 1994 - Aug 1998
Amirkabir University of Technology - Tehran Polytechnic 1991 - 1994
Iran University of Science and Technology Aug 1987 - May 1991
Technical high school of the Iranian Oil Ministry Aug 1983 - May 1987

Publications

Us Patents

Error Correcting Code Design For A Parity Enabled Memory

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US Patent:
20140047296, Feb 13, 2014
Filed:
Aug 9, 2012
Appl. No.:
13/571095
Inventors:
Iraj Motabar - Irvine CA, US
Morteza Cyrus Afghahi - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 13/05
G06F 11/10
US Classification:
714758, 714E11034
Abstract:
A memory system provides Error Correcting Code (ECC) protection for data stored in a parity enabled memory. The memory may include designated parity locations for data stored in the memory. During write operations, the system may obtain data to write into the memory, compute ECC protection bits for the data, and store the ECC protection bits in locations in the memory designated as parity locations for the data. During read operations, the system may read data from the memory. The system may also read protection bits for the data from locations designated as parity locations for the data. Then, the system may interpret the protection bits as ECC protection bits instead of as parity bits. The system may provide ECC protection for data without additional overhead or memory configuration changes to the parity enabled memory.

Robust Glitch-Free Clock Switch With An Unate Clock Network

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US Patent:
20120249194, Oct 4, 2012
Filed:
Mar 29, 2011
Appl. No.:
13/074689
Inventors:
Iraj MOTABAR - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03L 7/00
H03K 19/00
US Classification:
327153, 327141, 326 93
Abstract:
A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock.
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Iraj Living Tr Motabar from Laguna Niguel, CA, age ~56 Get Report