Ian D Kountanis

20120079249, Mar 29, 2012

Sep 28, 2010

12/892438

Wei-Han Lien - San Jose CA, US
Ian D. Kountanis - Santa Clara CA, US
Shyam Sundar - Sunnyvale CA, US

G06F 9/30

712212, 712E09016

In an embodiment, a decode unit includes multiple decoders configured to decode different types of instructions. One or more of the decoders may be complex decoders, and the decode unit may disable the complex decoders if an instruction of the corresponding type is not being decoded. In an embodiment, the decode unit may disable the complex decoders by data-gating the instruction into the decoder. The decode unit may also include a control unit that is configured to detect instructions of the type decoded by the complex decoders, and to enable the complex decoders and redirect the fetching in response to the detection. The decode unit may also record an indication of the instruction (e.g. the program counter address (PC) of the instruction) to more rapidly detect the instruction and prevent a redirect in subsequent fetches.

20130339699, Dec 19, 2013

Jun 15, 2012

13/524478

Ian D. Kountanis - Santa Clara CA, US

G06F 9/38

712241, 712E09045

Methods, apparatuses, and processors for packing multiple iterations of a loop in a loop buffer. A loop candidate that meets the criteria for buffering is detected in the instruction stream being executed by a processor. When the loop is being written to the loop buffer and the end of the loop is detected, another iteration of the loop is written to the loop buffer if the loop buffer is not yet halfway full. In this way, short loops are written to the loop buffer multiple times to maximize the instruction operations per cycle throughput out of the loop buffer when the processor is in loop buffer mode.

20130339700, Dec 19, 2013

Jun 15, 2012

13/524508

Ian D. Kountanis - Santa Clara CA, US

G06F 9/38

712241, 712E09045

Methods, apparatuses, and processors for tracking loop candidates in an instruction stream. A load buffer control unit detects a backwards taken branch and starts tracking the loop candidate. The control unit tracks taken branches of the loop candidate, and keeps track of the distance to each taken branch from the start of the loop. If the distance to each taken branch stays the same over multiple iterations of the loop, then the loop is stored in a loop buffer. The loop is then dispatched from the loop buffer, and the front-end of the processor is powered down until the loop terminates.

20120047329, Feb 23, 2012

Aug 23, 2010

12/861091

Rajat Goel - Saratoga CA, US
Ian D. Kountanis - Santa Clara CA, US

G06F 12/08
G06F 12/00

711125, 711E12001, 711E1202

In some embodiments, a cache may include a tag array and a data array, as well as circuitry that detects whether accesses to the cache are sequential (e.g., occupying the same cache line). For example, a cache may include a tag array and a data array that stores data, such as multiple bundles of instructions per cache line. During operation, it may be determined that successive cache requests are sequential and do not cross a cache line boundary. Responsively, various cache operations may be inhibited to conserve power. For example, access to the tag array and/or data array, or portions thereof, may be inhibited.

20230023860, Jan 26, 2023

Jul 21, 2021

17/382123

- Cupertino CA, US
Ian D. Kountanis - Santa Clara CA, US
Amit Kumar - Lake Oswego OR, US
Muawya M. Al-Otoom - Fremont CA, US

G06F 9/30
G06F 9/38
G06K 9/62

Techniques are disclosed relating to signature-based instruction prefetching. In some embodiments, processor pipeline circuitry executes a computer program that includes control transfer instructions, such that the execution follows a taken path through the computer program. First signature prefetch table circuitry indicates prefetch addresses for signatures generated using a first signature generation technique and second signature prefetch table circuitry that indicates prefetch addresses for signatures generated using a second, different signature generation technique. Signature prefetch circuitry, in response to a prefetch training event: determines a first signature according to the first technique and a second signature according to the second technique and selects one but not both of the first and second signature prefetch tables to train using the first signature or the second signature.

20230010948, Jan 12, 2023

Sep 16, 2022

17/932883

- Cupertino CA, US
Ian D. Kountanis - Santa Clara CA, US
Conrado Blasco - Sunnyvale CA, US
Steven Andrew Myers - San Jose CA, US
Yannick L. Sierra - San Francisco CA, US

G06F 9/38
G06F 21/60
G06F 9/455
G06F 9/30

A system and method for efficiently protecting branch prediction information. In various embodiments, a computing system includes at least one processor with a branch predictor storing branch target addresses and security tags in a table. The security tag includes one or more components of machine context. When the branch predictor receives a portion of a first program counter of a first branch instruction, and hits on a first table entry during an access, the branch predictor reads out a first security tag. The branch predictor compares one or more components of machine context of the first security tag to one or more components of machine context of the first branch instruction. When there is at least one mismatch, the branch prediction information of the first table entry is not used. Additionally, there is no updating of any branch prediction training information of the first table entry.

20210240476, Aug 5, 2021

Jan 31, 2020

16/778913

- Cupertino CA, US
Ian D. Kountanis - Santa Clara CA, US

G06F 9/38
G06F 9/30

In an embodiment, an indirect branch predictor generates indirect branch predictions for indirect branch instructions. For relatively static branch instructions, the indirect branch predictor may be configured to use a PC corresponding to the indirect branch instruction to generate a target prediction. The indirect branch predictor may be configured to identify at least one dynamic indirect branch instruction and may use a different PC than the PC corresponding to the indirect branch instruction to generate the target prediction (e.g. the most recent previous PC associated with a taken branch (“the previous taken PC”). For some dynamic indirect branch instructions, the previous taken PC may disambiguate different target addresses (e.g. there may be a correlation between the previous taken PC and the target address of the indirect branch instruction).

20210240477, Aug 5, 2021

Jan 31, 2020

16/778939

- Cupertino CA, US
Ian D. Kountanis - Santa Clara CA, US
Conrado Blasco - Sunnyvale CA, US
Haoyan Jia - Fremont CA, US
Amit Kumar - Fremont CA, US

G06F 9/38
G06F 9/30

In an embodiment, an indirect branch predictor generates indirect branch predictions based on one or more register values. The register values may be the contents of registers on which the indirect branch instruction is directly or indirectly dependent for generating the branch target address, for example. In an embodiment, at least one of the registers may be a source for a load instruction, and the indirect branch may be dependent (directly or indirectly) on the target of the load. In an embodiment, the indirect branch predictor may be one of at least two indirect branch predictors in a processor. The other indirect branch predictor may be based on a fetch address, or PC, associated with the indirect branch instruction. The other indirect branch predictor may generate a first predicted target address, and the indirect branch predictor may generate a second predicted target address for the same indirect branch instruction.