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Hessam Mahdavifar

from San Diego, CA
Age ~39
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Also known as:
Hessam R, Hessam A
Connected to:
Afshin H Mahdavi, 57Ashkan Mahdavi, 36Behnaz Mahdavi, 63Golnoosh Mahdavi, 31Kaveh Mahdavi, 42Majid Mahdavi, 56Saeid Mahdavi, 72Seyedmehdi Mahdavian, 66Soheil Mahdavian, 40Nadirah Mahdee, 40

Hessam Mahdavifar Phones & Addresses

  • San Diego, CA
  • Aurora, CO
  • Westminster, CO
  • Ann Arbor, MI
  • La Jolla, CA

Work

Company: Samsung Jul 2012 Address: Greater San Diego Area Position: Senior engineer

Education

Degree: PhD School / High School: University of California, San Diego 2007 to 2012 Specialities: Electrical Engineering - Communication Systems

Skills

Signal Processing • Matlab • Algorithms • C++ • Simulations • C • Latex • Image Processing • Digital Signal Processors • Python • Ofdm • Electrical Engineering • Mimo • Java • Wireless Communications Systems • Machine Learning • Information Theory • Coding Theory • Internet of Things • Game Theory

Industries

Telecommunications

Resumes

Resumes

Hessam Mahdavifar Photo 1

Assistant Professor

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Location:
5689 Versailles Ave, Ann Arbor, MI 48103
Industry:
Telecommunications
Work:
Samsung - Greater San Diego Area since Jul 2012
Senior Engineer
Hitachi GST Oct 2011 - Jan 2012
Storage Architecture Intern
Education:
University of California, San Diego 2007 - 2012
PhD, Electrical Engineering - Communication Systems Sharif University of Technology 2003 - 2007
BS, Electrical Engineering
Skills:
Signal Processing
Matlab
Algorithms
C++
Simulations
C
Latex
Image Processing
Digital Signal Processors
Python
Ofdm
Electrical Engineering
Mimo
Java
Wireless Communications Systems
Machine Learning
Information Theory
Coding Theory
Internet of Things
Game Theory

Publications

Us Patents

System And Method For Maximal Code Polarization

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US Patent:
20180145702, May 24, 2018
Filed:
Mar 15, 2017
Appl. No.:
15/459962
Inventors:
- Gyeonggi-do, KR
Mostafa EL-KHAMY - San Diego CA, US
Hessam MAHDAVIFAR - San Diego CA, US
International Classification:
H03M 7/30
H01L 21/66
G06F 17/50
H03M 13/01
Abstract:
An apparatus and a method. The apparatus includes a plurality of polarization processors, including n inputs and n outputs, where n is an integer; and at least one permutation processor, including n inputs and n outputs, wherein each of the at least one permutation processor is connected between two of the plurality of polarization processors, and connects the n outputs of a first of the two of the plurality of polarizations processors to the n inputs of a second of the two of the plurality of polarization processors between which each of the at least one permutation processor is connected in a permutation pattern that maximally polarizes the n outputs of the second of the two of the plurality of polarization processors.

System And Method For Encoding And Decoding Of Data With Channel Polarization Mechanism

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US Patent:
20150349909, Dec 3, 2015
Filed:
Oct 24, 2014
Appl. No.:
14/522924
Inventors:
- Suwon-si, KR
Hessam Mahdavifar - San Diego CA, US
Gennady Feygin - San Diego CA, US
Jungwon Lee - San Diego CA, US
Inyup Kang - San Diego CA, US
International Classification:
H04J 13/00
H04W 72/04
H04J 13/10
Abstract:
A computing system includes: a communication unit configured to: determine a relaxed coding profile including a polar-processing range for processing content data over a bit channel; process the content data based on a total polarization level being within the polar-processing range, the polar-processing range for controlling a polar processing mechanism or a portion therein corresponding to the bit channel for the content data; and an inter-device interface, coupled to the communication unit, configured to communicate the content data.

Techniques For Encoding And Decoding Using A Combinatorial Number System

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US Patent:
20140164821, Jun 12, 2014
Filed:
Dec 12, 2012
Appl. No.:
13/712929
Inventors:
- Amsterdam, NL
Luiz Franca-Neto - Sunnyvale CA, US
Robert Eugeniu Mateescu - San Jose CA, US
Hessam Mahdavifar - San Diego CA, US
Zvonimir Bandic - San Jose CA, US
Qingbo Wang - Irvine CA, US
Assignee:
HGST NETHERLANDS B.V. - Amsterdam
International Classification:
G06F 11/07
US Classification:
714 611
Abstract:
A data storage system includes a memory circuit having memory cells and a control circuit. The control circuit is operable to receive data bits provided for storage in the memory cells. A subset of the memory cells have predetermined stuck-at faults. The control circuit is operable to compute a binomial coefficient for each of the predetermined stuck-at faults based on a bit position of a corresponding one of the predetermined stuck-at faults within the memory cells. The control circuit is operable to add together the binomial coefficients to generate an encoded number using a combinatorial number system. The control circuit is operable to generate a first set of redundant bits that indicate the encoded number. The first set of redundant bits are used to decode bits read from the memory cells to regenerate the data bits.

Encoding And Decoding Data To Accommodate Memory Cells Having Stuck-At Faults

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US Patent:
20140101516, Apr 10, 2014
Filed:
Oct 10, 2012
Appl. No.:
13/649098
Inventors:
- Amsterdam, NL
Luiz Franca-Neto - Sunnyvale CA, US
Cyril Guyot - San Jose CA, US
Hessam Mahdavifar - San Diego CA, US
Zvonimir Bandic - San Jose CA, US
Qingbo Wang - Irvine CA, US
Assignee:
HGST NETHERLANDS B.V. - Amsterdam
International Classification:
G06F 11/10
H03M 13/15
US Classification:
714766, 714E11034
Abstract:
A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix. Each row of the first matrix corresponds to a unique one of the data bits. The control circuit is operable to generate a second matrix having only the rows of the first matrix that correspond to the data bits provided for storage in a subset of the memory cells having stuck-at faults. The control circuit is operable to generate a third matrix having linearly independent columns of the second matrix. The control circuit is operable to encode the data bits to generate encoded data bits and redundant bits using the third matrix.

Encoding And Decoding Redundant Bits To Accommodate Memory Cells Having Stuck-At Faults

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US Patent:
20140101517, Apr 10, 2014
Filed:
Oct 10, 2012
Appl. No.:
13/649108
Inventors:
- Amsterdam, NL
Luiz Franca-Neto - Sunnyvale CA, US
Cyril Guyot - San Jose CA, US
Hessam Mahdavifar - San Diego CA, US
Zvonimir Bandic - San Jose CA, US
Qingbo Wang - Irvine CA, US
Assignee:
HGST NETHERLANDS B.V. - Amsterdam
International Classification:
G06F 11/10
US Classification:
714766, 714E11034
Abstract:
A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.
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Hessam Mahdavifar from San Diego, CA, age ~39 Get Report