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Henrik P Esbensen

from Vista, CA
Age ~60
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Also known as:
Hendrik P Esbensen, Henrick Esbensen, Henrik Esbenson
Phone and address:
941 Bellwood Ln, Vista, CA 92081
(760) 727-5604
Related to:
Pia Esbensen, 59
Connected to:
Diana L Esbensen, 58Gloria A Esbensen, 68Eric W Esbenshade, 55Hannah Esbenshade, 35Kimberly J Esbenshade, 64Melissa K Esber, 60Steven J Esber, 63Donald L Esbin, 81Eric S Esbitt, 63Milton Esbitt, 85

Henrik Esbensen Phones & Addresses

  • 941 Bellwood Ln, Vista, CA 92081 (760) 727-5604
  • 45112 Lynx Ct, Fremont, CA 94539 (510) 623-7440
  • El Cerrito, CA
  • Hayward, CA
  • San Marcos, CA
  • Pleasant Hill, CA
  • Ann Arbor, MI
  • San Diego, CA

Work

Company: Wave computing May 2018 Position: Senior director, software tools

Education

School / High School: University of California, Berkeley 1994 to 1996 Specialities: Computer Science

Skills

Algorithms • Eda • C++ • Tcl • Software Engineering • Linux • Software Development • Object Oriented Design • Optimization • Python • Data Structures • Scripting • Object Oriented Modeling • Engineering Management • Physical Design • Heuristics • Stl • Eclipse • Product Design

Industries

Computer Software

Resumes

Resumes

Henrik Esbensen Photo 1

Chief Technology Officer And Co-Founder

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Location:
San Diego, CA
Industry:
Computer Software
Work:
Wave Computing
Senior Director, Software Tools
Wave Computing Jun 2012 - May 2018
Distinguished Member of Technical Staff
Dreamstart Labs Jun 2012 - May 2018
Chief Technology Officer and Co-Founder
Magma Design Automation 2004 - 2012
Software Architect
Magma Design Automation 2002 - 2003
Member of Consulting Staff
Education:
University of California, Berkeley 1994 - 1996
Aarhus University 1984 - 1994
Doctorates, Doctor of Philosophy, Computer Science University of Michigan 1992 - 1993
Aarhus University 1984 - 1988
Bachelors, Bachelor of Science, Mathematics
Skills:
Algorithms
Eda
C++
Tcl
Software Engineering
Linux
Software Development
Object Oriented Design
Optimization
Python
Data Structures
Scripting
Object Oriented Modeling
Engineering Management
Physical Design
Heuristics
Stl
Eclipse
Product Design

Business Records

Name / Title
Company / Classification
Phones & Addresses
Henrik Esbensen
President
ELEVATE AFRICA
663 S Rancho Santa Fe Rd STE 258, San Marcos, CA 92078
12529 El Camino Real, San Diego, CA 92130

Publications

Us Patents

Relative Floorplanning For Improved Integrated Circuit Design

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US Patent:
20070266359, Nov 15, 2007
Filed:
May 14, 2007
Appl. No.:
11/748416
Inventors:
Henrik Esbensen - Vista CA, US
Roger Carpenter - Palo Alto CA, US
Cornelis Van Eijk - Hilvarenbeek, NL
Assignee:
Magma Design Automation, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716010000
Abstract:
A method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A relative floorplanning constraint is extracted from the floorplan design. The floorplan of the integrated circuit is updated in response to the relative floorplanning constraint. Another method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A set of relative floorplanning constraint is received from the floorplan design. A relative floorplanning constraint is pushed down from the set of relative floorplanning constraints into a partition associated with the floorplan of the integrated circuit. The floorplan is updated in response to the set of relative floorplanning constraints.

Reconfigurable Computing Resource Allocation Using Flow Graph Translation

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US Patent:
20180341734, Nov 29, 2018
Filed:
Aug 1, 2018
Appl. No.:
16/051854
Inventors:
- Campbell CA, US
Henrik Esbensen - Vista CA, US
Kenneth Shiring - San Jose CA, US
Peter Ramyalal Suaris - Woodland Hills CA, US
International Classification:
G06F 17/50
Abstract:
Systems and methods are disclosed for computing resource configuration based on flow graph translation. First, a high-level description of logic circuitry is obtained and translated to generate a flow graph representing sequential operations. Using the flow graph, similar processing elements in an array are interchangeably configured to perform computational, communication, and storage tasks as needed. The sequential operations are executed using the array of interchangeable processing elements. Data is provided from the storage elements through the communication elements to the computational elements. Computational results are stored in the storage elements. Outputs from some of the computational elements provide inputs to other computational elements. Execution of the instructions can be controlled with time stepping. The processors are reconfigured as needed, based on changes to the flow graph, on subsequent time steps.

Computing Resource Allocation Based On Flow Graph Translation

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US Patent:
20160125118, May 5, 2016
Filed:
Oct 30, 2015
Appl. No.:
14/928314
Inventors:
- Campbell CA, US
Henrik Esbensen - Vista CA, US
Kenneth Shiring - San Jose CA, US
Peter Ramyalal Suaris - Woodland Hills CA, US
International Classification:
G06F 17/50
Abstract:
Systems and methods are disclosed for computing resource allocation based on flow graph translation. First, a high-level description of logic circuitry is obtained and translated to generate a flow graph representing sequential operations. Using the flow graph, similar processing elements in an array are interchangeably allocated to perform computational, communication, and storage tasks as needed. The sequential operations are executed using the array of interchangeable processing elements. Data is provided from the storage elements through the communication elements to the computational elements. Computational results are stored in the storage elements. Outputs from some of the computational elements provide inputs to other computational elements. Execution of the instructions can be controlled with time stepping. The processors are reallocated as needed, based on changes to the flow graph.
Control profile
Henrik P Esbensen from Vista, CA, age ~60 Get Report