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Giuseppina Puzzilli

from Boise, ID
Age ~49
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Connected to:
Jon T Puzzo, 42Joseph C Puzzo, 46Madeline E Puzzo, 34Jeffrey Puzzullo, 69Avilynn Pwyll, 71David E Py, 66Gregory Py, 37Michel Py, 53Richard M Py, 71Madhavi Pyakurel, 35

Giuseppina Puzzilli Phones & Addresses

  • 2881 S Swallowtail Ln, Boise, ID 83706

Skills

Electrical Characterization • Non Volatile Memories • Semiconductor Process Integration • Reliability • Statistics • Cross Functional Team Working • Design of Experiment • Bench Data Collection • Characterization • Semiconductor Process • Silicon • R&D • Cmos • Design of Experiments • Process Integration • Microelectronics • Semiconductors • Ic • Thin Films • Semiconductor Industry • Device Characterization • Jmp • Simulations

Industries

Semiconductors

Resumes

Resumes

Giuseppina Puzzilli Photo 1

Giuseppina Puzzilli

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Location:
Boise, ID
Industry:
Semiconductors
Skills:
Electrical Characterization
Non Volatile Memories
Semiconductor Process Integration
Reliability
Statistics
Cross Functional Team Working
Design of Experiment
Bench Data Collection
Characterization
Semiconductor Process
Silicon
R&D
Cmos
Design of Experiments
Process Integration
Microelectronics
Semiconductors
Ic
Thin Films
Semiconductor Industry
Device Characterization
Jmp
Simulations

Publications

Us Patents

Erase Operations And Apparatus For A Memory Device

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US Patent:
8369158, Feb 5, 2013
Filed:
Dec 23, 2009
Appl. No.:
12/646136
Inventors:
Akira Goda - Boise ID, US
Giuseppina Puzzilli - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518529, 365218
Abstract:
Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the memory cells to a second bias potential and biasing access lines of one or more remaining memory cells to a third potential. A ramping bias potential is applied to channel regions of the string of memory cells substantially concurrently with or subsequent to biasing the select gate control lines and the access lines, and floating the select gate control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.

In-Field Block Retiring

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US Patent:
8514624, Aug 20, 2013
Filed:
Jun 21, 2011
Appl. No.:
13/165416
Inventors:
Krishna K. Parat - Palo Alto CA, US
Akira Goda - Boise ID, US
Koichi Kawai - Kanagawa, JP
Brian J. Soderling - Eagle ID, US
Jeremy Binfet - Boise ID, US
Arnaud A. Furnemont - Boise ID, US
Tejas Krishnamohan - Mountain View CA, US
Tyson M. Stichka - Boise ID, US
Giuseppina Puzzilli - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 16/04
US Classification:
36518517, 36518522, 36518529
Abstract:
Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

Data Line Management In A Memory Device

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US Patent:
8619474, Dec 31, 2013
Filed:
Sep 10, 2009
Appl. No.:
12/556941
Inventors:
Akira Goda - Boise ID, US
Andrew Bicksler - Boise ID, US
Violante Moschiano - Bacoli, IT
Giuseppina Puzzilli - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/02
US Classification:
36518519, 365195
Abstract:
Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.

Memory Array Having Memory Cells Coupled Between A Programmable Drain Select Gate And A Non-Programmable Source Select Gate

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US Patent:
20110199827, Aug 18, 2011
Filed:
Feb 17, 2010
Appl. No.:
12/707162
Inventors:
Giuseppina Puzzilli - Boise ID, US
Andrew Bicksler - Boise ID, US
Akira Goda - Boise ID, US
International Classification:
G11C 16/04
G11C 16/06
US Classification:
36518514, 36518517, 3651852, 36518529
Abstract:
Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of series-coupled memory cells, and a programmable select gate coupled in series to a second end of the string of series-coupled memory cells.

In-Field Block Retiring

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US Patent:
20130332769, Dec 12, 2013
Filed:
Aug 19, 2013
Appl. No.:
13/970055
Inventors:
Akira Goda - Boise ID, US
Koichi Kawai - Yokohama, JP
Brian J. Soderling - Eagle ID, US
Jeremy Binfet - Boise ID, US
Arnaud A. Furnemont - Boise ID, US
Tejas Krishnamohan - Mountain View CA, US
Tyson M. Stichka - Boise ID, US
Giuseppina Puzzilli - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 29/00
US Classification:
714 613
Abstract:
Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

Adjusting A Preprogram Voltage Based On Use Of A Memory Device

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US Patent:
20220391125, Dec 8, 2022
Filed:
Aug 18, 2022
Appl. No.:
17/890885
Inventors:
- Boise ID, US
Pitamber Shukla - Boise ID, US
Scott A. Stoller - Boise ID, US
Giuseppina Puzzilli - Boise ID, US
International Classification:
G06F 3/06
Abstract:
A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

Implementing Fault Tolerant Page Stripes On Low Density Memory Systems

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US Patent:
20220357873, Nov 10, 2022
Filed:
Jul 25, 2022
Appl. No.:
17/872206
Inventors:
- Boise ID, US
Mark A. Helm - Santa Cruz CA, US
Giuseppina Puzzilli - Boise ID, US
Peter Feeley - Boise ID, US
Yifen Liu - Boise ID, US
Violante Moschiano - Avezzano, IT
Akira Goda - Tokyo, JP
Sampath K. Ratnam - San Jose CA, US
International Classification:
G06F 3/06
Abstract:
An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Separate Partition For Buffer And Snapshot Memory

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US Patent:
20220350517, Nov 3, 2022
Filed:
Jun 22, 2022
Appl. No.:
17/846462
Inventors:
- Boise ID, US
Akira Goda - Boise ID, US
Todd A. Marquart - Boise ID, US
Mark A. Helm - Santa Cruz CA, US
Gil Golov - Backnang, DE
Jeremy Binfet - Boise ID, US
Carmine Miccoli - Boise ID, US
Giuseppina Puzzilli - Boise ID, US
International Classification:
G06F 3/06
Abstract:
A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.
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Giuseppina Puzzilli from Boise, ID, age ~49 Get Report