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Gill Yong Lee

from San Jose, CA
Age ~58
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Also known as:
Gill Y Lee, Yong Lee Gill, Gill Gill, Lee Y Gill
Related to:
Marsha C Lee, 32Sarah Lee, 31Jessica Lee, 79Young Lee, 68
Connected to:
Abbe Lee, 111Abe H Lee, 38Aben A Lee, 46Adah Y Lee, 59Adam Lee, 56Aditi D Lee, 42Ah C Lee, 69Ah Lee, 38Ahiliya Lee, 61Aireosha Lee, 70

Gill Lee Phones & Addresses

  • San Jose, CA
  • Santa Clara, CA
  • Palo Alto, CA
  • Richmond, VA
  • Hopewell Junction, NY
  • Santa Clarita, CA
  • Wappingers Falls, NY
  • 48 Sandy Pines Blvd, Hopewell Junction, NY 12533

Education

Degree: Graduate or professional degree

Resumes

Resumes

Gill Lee Photo 1

Gill Lee

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Location:
Santa Clara, CA
Industry:
Electrical/Electronic Manufacturing
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Gill Lee

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Publications

Us Patents

Method For Low Temperature Chemical Vapor Deposition Of Low-K Films Using Selected Cyclosiloxane And Ozone Gases For Semiconductor Applications

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US Patent:
6531412, Mar 11, 2003
Filed:
Aug 10, 2001
Appl. No.:
09/928209
Inventors:
Richard A. Conti - Katonah NY
Daniel C. Edelstein - White Plains NY
Gill Yong Lee - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich
International Classification:
H01C 2131
US Classification:
438778, 438695, 438697, 438712, 438723, 438761, 438781, 438618, 438620, 438622, 438626, 438627, 438628, 42725528, 42725539, 427255393, 427569, 427578, 427579
Abstract:
A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Carbon-Graded Layer For Improved Adhesion Of Low-K Dielectrics To Silicon Substrates

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US Patent:
6570256, May 27, 2003
Filed:
Jul 20, 2001
Appl. No.:
09/910380
Inventors:
Richard A. Conti - Mount Kisco NY
Prakash Chimanlal Dev - Plano TX
David M. Dobuzinsky - New Windsor NY
Daniel C. Edelstein - White Plains NY
Gill Y. Lee - Wappingers Falls NY
Padraic C. Shafer - Beacon NY
Alexander Simpson - Wappingers Falls NY
Peter Wrschka - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2348
US Classification:
257761, 257760, 257752, 257 72, 257762, 257767, 438624, 438622
Abstract:
A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3. 3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Removable Inorganic Anti-Reflection Coating Process

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US Patent:
6607984, Aug 19, 2003
Filed:
Jun 20, 2000
Appl. No.:
09/597122
Inventors:
Gill Yong Lee - Wappingers Falls NY
Scott D. Halle - Hopewell Junction NY
Jochen Beintner - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich
International Classification:
H01L 21302
US Classification:
438700, 438723, 438724
Abstract:
In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

Process For Forming A Damascene Structure

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US Patent:
6649531, Nov 18, 2003
Filed:
Nov 26, 2001
Appl. No.:
09/994340
Inventors:
William J. Cote - Poughkeepsie NY
Timothy J. Dalton - Ridgefield CT
Prakash Chimanlal Dev - Plano TX
Daniel C. Edelstein - White Plains NY
Scott D. Halle - Hopewell Junction NY
Gill Yong Lee - Wappingers Falls NY
Arpan P. Mahorowala - Bronxville NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21302
US Classification:
438714, 438725
Abstract:
A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

Magnetic Tunnel Junction Patterning Using Sic Or Sin

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US Patent:
6713802, Mar 30, 2004
Filed:
Jun 20, 2003
Appl. No.:
10/600661
Inventors:
Gill Yong Lee - Wappingers Falls NY
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 2100
US Classification:
257295, 257303, 257421, 438 3, 438253
Abstract:
A material that is harder than silicon dioxide is used as a hard mask to pattern the soft layer of an MTJ stack of a magnetic memory device, which increases the process window for post-MTJ stack planarization. The soft layer hard mask material may comprise SiC, SiON, SiCN or SiN or another dielectric material having a Youngs modulus greater than the Youngs modulus of silicon dioxide. A hard fill dielectric material is also used as an insulating material over the hard mask used to pattern the soft layer. The fill dielectric material may also comprise SiC, SiON, SiCN or SiN or another dielectric material having a Youngs modulus greater than the Youngs modulus of silicon dioxide.

Carbon-Graded Layer For Improved Adhesion Of Low-K Dielectrics To Silicon Substrates

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US Patent:
6740539, May 25, 2004
Filed:
Feb 13, 2003
Appl. No.:
10/366149
Inventors:
Richard A. Conti - Mount Kisco NY
Prakash Chimanlal Dev - Plano TX
David M. Dobuzinsky - New Windsor NY
Daniel C. Edelstein - White Plains NY
Gill Y. Lee - Wappingers Falls NY
Padraic C. Shafer - Beacon NY
Alexander Simpson - Wappingers Falls NY
Peter Wrschka - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
Infineon Technologies A.G.
International Classification:
H01L 5140
US Classification:
438 99, 438624, 438780
Abstract:
A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3. 3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Subtractive Stud Formation For Mram Manufacturing

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US Patent:
6783999, Aug 31, 2004
Filed:
Jun 20, 2003
Appl. No.:
10/600057
Inventors:
Gill Yong Lee - Wappingers Falls NY
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 2100
US Classification:
438 3
Abstract:
A method of fabricating a magnetic memory cell and an MRAM structure. A thin conductive hard is used to pattern a magnetic stack material layer. Conductive studs are fully landed on the top of the thin conductive hard mask, preventing the magnetic memory cells from being exposed subsequent etchant chemistries. The conductive studs provide a large process window for the upper level wiring trench formation, and also provide etch selectivity during the patterning of the upper level wiring.

Integration Scheme For Avoiding Plasma Damage In Mram Technology

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US Patent:
6806096, Oct 19, 2004
Filed:
Jun 18, 2003
Appl. No.:
10/464226
Inventors:
Woosik Kim - Wappingers Falls NY
Gill Yong Lee - Wappingers Falls NY
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 2100
US Classification:
438 3
Abstract:
A method of fabricating a magnetic memory device and a magnetic memory device structure. A buffer insulating layer is deposited over the top surface of the conductive hard mask of a magnetic memory cell. The buffer insulating layer is left remaining over the conductive hard mask top surface while the various material layers of the device are patterned and etched. The buffer insulating layer prevents the conductive hard mask top surface from being damaged during plasma-containing processes.
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Gill Yong Lee from San Jose, CA, age ~58 Get Report