Resumes
Resumes
Gill Lee Phones & Addresses
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902 Del Paso Blvd, Sacramento, CA 95815 (916) 929-5859
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Carmichael, CA
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65 Las Quebradas, Alamo, CA 94507 (925) 820-3737
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Piedmont, CA
Publications
Us Patents
Methods Of Forming Memory Device With Reduced Resistivity
View pageUS Patent:
20220415651, Dec 29, 2022
Filed:
Jun 29, 2021
Appl. No.:
17/361925
Inventors:
- Santa Clara CA, US
Chuanxi Yang - Los Altos CA, US
Hang Yu - San Jose CA, US
Deenesh Padhi - Sunnyvale CA, US
Gill Yong Lee - San Jose CA, US
Sung-Kwan Kang - San Jose CA, US
Abdul Wahab Mohammed - Santa Clara CA, US
Hailing Liu - Union City CA, US
Chuanxi Yang - Los Altos CA, US
Hang Yu - San Jose CA, US
Deenesh Padhi - Sunnyvale CA, US
Gill Yong Lee - San Jose CA, US
Sung-Kwan Kang - San Jose CA, US
Abdul Wahab Mohammed - Santa Clara CA, US
Hailing Liu - Union City CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/02
H01L 21/033
H01L 27/108
H01L 21/033
H01L 27/108
Abstract:
Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.
Gap Fill Methods For Dram
View pageUS Patent:
20200286897, Sep 10, 2020
Filed:
Feb 28, 2020
Appl. No.:
16/804226
Inventors:
- Santa Clara CA, US
Seshadri Ganguli - Sunnyvale CA, US
Sang Ho Yu - Cupertino CA, US
Sung-Kwan Kang - San Jose CA, US
Gill Yong Lee - San Jose CA, US
Sanjay Natarajan - Portland OR, US
Rajib Lochan Swain - Sunnyvale CA, US
Jorge Pablo Fernandez - Saratoga CA, US
Seshadri Ganguli - Sunnyvale CA, US
Sang Ho Yu - Cupertino CA, US
Sung-Kwan Kang - San Jose CA, US
Gill Yong Lee - San Jose CA, US
Sanjay Natarajan - Portland OR, US
Rajib Lochan Swain - Sunnyvale CA, US
Jorge Pablo Fernandez - Saratoga CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 27/108
Abstract:
Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
Cap Layer For Bit Line Resistance Reduction
View pageUS Patent:
20200235104, Jul 23, 2020
Filed:
Apr 3, 2020
Appl. No.:
16/839392
Inventors:
- Santa Clara CA, US
Jianxin Lei - Fremont CA, US
Wenting Hou - San Jose CA, US
Mihaela Balseanu - Sunnyvale CA, US
Ning Li - San Jose CA, US
Sanjay Natarajan - Portland OR, US
Gill Yong Lee - San Jose CA, US
In Seok Hwang - Pleasanton CA, US
Nobuyuki Sasaki - Cupertino CA, US
Sung-Kwan Kang - San Jose CA, US
Jianxin Lei - Fremont CA, US
Wenting Hou - San Jose CA, US
Mihaela Balseanu - Sunnyvale CA, US
Ning Li - San Jose CA, US
Sanjay Natarajan - Portland OR, US
Gill Yong Lee - San Jose CA, US
In Seok Hwang - Pleasanton CA, US
Nobuyuki Sasaki - Cupertino CA, US
Sung-Kwan Kang - San Jose CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 27/108
H01L 21/3213
H01L 21/033
H01L 21/3213
H01L 21/033
Abstract:
Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.
Cap Layer For Bit Line Resistance Reduction
View pageUS Patent:
20200126996, Apr 23, 2020
Filed:
Oct 18, 2018
Appl. No.:
16/164236
Inventors:
- Santa Clara CA, US
Jianxin Lei - Fremont CA, US
Wenting Hou - San Jose CA, US
Ning Li - San Jose CA, US
Sanjay Natarajan - Portland OR, US
Gill Yong Lee - San Jose CA, US
In Seok Hwang - Pleasanton CA, US
Nobuyuki Sasaki - Santa Clara CA, US
Sung-Kwan Kang - San Jose CA, US
Jianxin Lei - Fremont CA, US
Wenting Hou - San Jose CA, US
Ning Li - San Jose CA, US
Sanjay Natarajan - Portland OR, US
Gill Yong Lee - San Jose CA, US
In Seok Hwang - Pleasanton CA, US
Nobuyuki Sasaki - Santa Clara CA, US
Sung-Kwan Kang - San Jose CA, US
International Classification:
H01L 27/108
H01L 21/033
H01L 21/3213
H01L 21/033
H01L 21/3213
Abstract:
Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.