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Gernot Guenther Phones & Addresses

  • Austin, TX
  • 310 Boswell Hill Rd, Endicott, NY 13760
  • Vestal, NY
  • Buffalo, NY

Publications

Us Patents

Asic Based Conveyor Belt Style Programmable Cross-Point Switch Hardware Accelerated Simulation Engine

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US Patent:
7562320, Jul 14, 2009
Filed:
Sep 15, 2006
Appl. No.:
11/532248
Inventors:
Gernot E. Guenther - Endicott NY,
Viktor Sandor Gyuris - Wappingers Falls NY,
Thomas J. Tryt - Binghamton NY,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 1, 716 5, 716 18, 703 13, 703 14, 703 23, 703 24, 703 25
Abstract:
An ASIC based hardware accelerated simulation engine accelerates logic verification of integrated circuit designs utilizing a field of ASIC chips interconnected by direct connections. Communication between the chips has to be accomplished by switching technology internal to the chips. The switching technology employing programmable cross-point switches; i. e. hardware elements with input, output and command ports which propagate signals from the input ports to the output ports following a given permutation determined by values on the command port. The ASIC chip contains an instruction memory to program the logic elements thereof. A conveyor belt based implementation of the programmable cross-point switches provides reduced command bit requirements.

Hardware Accelerator With A Single Partition For Latches And Combinational Logic

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US Patent:
7769577, Aug 3, 2010
Filed:
Aug 31, 2007
Appl. No.:
11/848489
Inventors:
Gernot E. Guenther - Endicott NY,
Viktor Gyuris - Wappingers Falls NY,
Harrell Hoffman - Austin TX,
Kevin Anthony Pasnik - Westford VT,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
703 13, 703 14, 703 15, 703 16, 703 19, 703 21, 716 1, 716 4, 716 6
Abstract:
A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Concealment Of External Array Accesses In A Hardware Simulation Accelerator

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US Patent:
7877249, Jan 25, 2011
Filed:
Jan 12, 2006
Appl. No.:
11/330685
Inventors:
Gernot Eberhard Guenther - Endicott NY,
Vikto Gyuris - Wappingers Falls NY,
Thomas John Tryt - Binghamton NY,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/45
G06F 9/455
G06F 9/44
G06F 13/00
G06F 13/14
G06G 13/18
US Classification:
703 22, 711150, 711151, 711158
Abstract:
A circuit arrangement and method detect external requests to access a memory array in a hardware simulation accelerator during performance of a simulation on a simulation model and access the memory array without halting the simulation in response to detecting the external request. Such functionality may be provided, for example, by detecting such external requests in response to processing a predetermined instruction in an instruction stream associated with the simulation model, where the predetermined instruction is configured to ensure a predetermined period of inactivity for the memory array. By doing so, the memory array can be accessed from outside of the hardware simulation accelerator during the processing of a simulation, and without requiring that the simulation be halted, thus reducing overhead and improving simulation efficiency.

Hardware Simulation Accelerator Design And Method That Exploits A Parallel Structure Of User Models To Support A Larger User Model Size

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US Patent:
7945433, May 17, 2011
Filed:
Apr 30, 2007
Appl. No.:
11/742100
Inventors:
Gernot E. Guenther - Endicott NY,
Viktor Gyuris - Wappingers Falls NY,
Harrell Hoffman - Austin TX,
Kevin A. Pasnik - Cedar Park TX,
Thomas J. Tryt - Binghamton NY,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/445
G06F 9/30
US Classification:
703 14, 703 26, 717140, 712 20
Abstract:
A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.

Hardware Accelerator With A Single Partition For Latches And Combinational Logic

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US Patent:
2006019, Aug 24, 2006
Filed:
Feb 24, 2005
Appl. No.:
11/064727
Inventors:
Gernot Guenther - Endicott NY,
Viktor Gyuris - Wappingers Falls NY,
Harrell Hoffman - Austin TX,
Kevin Pasnik - Westford VT,
John Westermann - Endicott NY,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
703015000
Abstract:
A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Real-Time Data Stream Decompressor

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US Patent:
2008012, May 29, 2008
Filed:
Oct 27, 2006
Appl. No.:
11/553605
Inventors:
Gernot E. Guenther - Endicott NY,
Viktor S. Gyuris - Wappingers Falls NY,
Thomas J. Tryt - Binghamton NY,
John H. Westermann - Endicott NY,
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 703 16, 716 16
Abstract:
Method, system, and program product for expanding the effective capacity of embedded memory by storing data in a compressed form and reading the data out with subsequent data decompression, including adaptive decompression and data conversion. The system and method for compression and decompression of HDL code between HDL code storage and HDL code processing for simulation of a device or system.

Instruction Encoding In A Hardware Simulation Accelerator

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US Patent:
2008024, Oct 2, 2008
Filed:
Mar 30, 2007
Appl. No.:
11/694940
Inventors:
Gernot E. Guenther - Endicott NY,
Viktor Gyuris - Wappingers Falls NY,
Kevin Anthony Pasnik - Cedar Park TX,
Thomas John Tryt - Binghamton NY,
John H. Westermann - Endicott NY,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
703 15
Abstract:
A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.
Gernot E Guenther from Austin, TX, age ~46 Get Report