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Gary Vondran Phones & Addresses

  • San Francisco, CA
  • 1905 Quail Meadow Rd, Los Altos Hills, CA 94024 (650) 941-2312 (650) 941-7477 (650) 941-8894
  • Los Altos, CA
  • Cadiz, CA
  • Santa Clara, CA

Resumes

Resumes

Gary Vondran Photo 1

Gary Vondran

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Position:
Senior Principal Engineer, Multimedia Systems and Architecture at Broadcom
Location:
San Francisco Bay Area
Industry:
Research
Work:
Broadcom since Sep 2012
Senior Principal Engineer, Multimedia Systems and Architecture

Hewlett-Packard Laboratories Dec 2011 - Sep 2012
Principal Scientist

Hewlett-Packard Co. Aug 2006 - Dec 2011
Principal Scientist

Hewlett-Packard Laboratories Aug 2001 - Aug 2006
Senior Scientist & Lab Section Manager

Hewlett-Packard Laboratories Aug 1999 - Aug 2001
Senior Scientist & Research Manager
Education:
Massachusetts Institute of Technology - Sloan School of Management 2007 - 2009
Executive Certificate, Business and Corporate Strategy
Carnegie Mellon University 1993 - 1995
MS, Computer Engineering
Stanford University 1988 - 1993
Graduate Certificate, Computer Engineering
California Institute of Technology 1988
BS, Electrical Engineering
Skills:
Programming
Parallel Algorithms
Computer Architecture
Algorithms
Parallel Computing
Processors
Optimization
Scalability
Imaging
Image Processing
High Performance Computing
C
Architecture
Embedded Systems
Digital Imaging
Debugging
C/C++
OpenCL
GPU
GPGPU
CUDA
Technical Management
OpenCV
Renderscript
Computer Hardware
Software Engineering
Microprocessors
Data Mining
Gary Vondran Photo 2

Sw Engineering Manager Ii

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Location:
San Francisco, CA
Industry:
Research
Work:
Apple
Imaging Scientist, Camera Architecture

Broadcom Sep 2012 - Jul 2014
Senior Principal Engineer

Hewlett-Packard Aug 2006 - Dec 2011
Principal Scientist

Hewlett-Packard Aug 1999 - Aug 2001
Senior Scientist and Senior Research Manager

Hewlett-Packard Mar 1996 - Aug 1999
Senior Research Scientist
Education:
Mit Sloan School of Management 2007 - 2009
Carnegie Mellon University 1993 - 1995
Master of Science, Masters, Computer Engineering
Stanford University 1988 - 1993
Caltech 1988 - 1988
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Algorithms
High Performance Computing
Image Processing
Computer Architecture
System Architecture
Digital Imaging
Software Engineering
C
Processors
Embedded Systems
R&D
Computer Vision
Scalability
Computer Science
Distributed Systems
Asic
Architecture
Data Mining
Debugging
Signal Processing
Digital Signal Processors
Parallel Computing
Optimization
Programming
Soc
Firmware
C++
Microprocessors
Hardware Architecture
Parallel Algorithms
Imaging
Gpgpu
Cuda
Computer Hardware
Pattern Recognition
Fpga
Simulations
Embedded Software
Perl
Device Drivers
Verilog
Linux Kernel
Arm
Sensors
Compilers
Matlab
Opencl
Opencv
Opengl
Augmented Reality
Gary Vondran Photo 3

Fiber Reinforcing And Eps Concrete Consultant

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Location:
1235 Ellis St, San Francisco, CA 94109
Industry:
Construction
Work:
Consultant since Jan 2011
Fiber Reinforcing & EPS Concrete Consultant

self - Northern California---Silicon Valley USA since Jan 1990
consultant

VonTech International Corp 1994 - Jan 2007
President

Fibermesh Div. of Synthetic Industries - San Jose & Campbell, CA Mar 1985 - Jan 1990
Director of Research & Development
Education:
San Jose State University 1978 - 1978
UC Berkeley 1974 - 1974
B.A., Economics
University of Notre Dame 1955 - 1959
Skills:
Contractors
Subcontracting
Renovation
Concrete
Value Engineering
Residential
Interests:
Home Improvement
Collecting
Home Decoration
Languages:
English
Gary Vondran Photo 4

Senior Consultant

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Location:
San Francisco, CA
Industry:
Information Technology And Services
Work:
Self Employed
Senior Consultant

Business Records

Name / Title
Company / Classification
Phones & Addresses
Gary L. Vondran
President
VON TEST INTERNATIONAL
1905 Quail Mdw Rd, Los Altos, CA 94024
Gary L. Vondran
President
VONTECH INTERNATIONAL CORPORATION
1905 Quail Mdw Rd, Los Altos, CA 94024

Publications

Us Patents

Chip Multiprocessor With Multiple Operating Systems

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US Patent:
6874014, Mar 29, 2005
Filed:
May 29, 2001
Appl. No.:
09/865605
Inventors:
Stephen E. Richardson - Los Altos CA, US
Gary Vondran - San Carlos CA, US
Stuart Siu - Castro Valley CA, US
Paul Keltcher - Sunnyvale CA, US
Shankar Venkataraman - Cupertino CA, US
Padmanabha Venkitakrishnan - Sunnyvale CA, US
Joseph Ku - Palo Alto CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F011/00
US Classification:
709213, 709222, 711173, 713 2, 718 1, 719313
Abstract:
Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.

Computer Instruction Dispatch

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US Patent:
7139897, Nov 21, 2006
Filed:
Apr 1, 2002
Appl. No.:
10/113074
Inventors:
Paul Keltcher - Sunnyvale CA, US
Gary Vondran - San Carlos CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 15/00
US Classification:
712 24, 712211
Abstract:
Circuit arrangement and method for dispatching computer instructions. In a processor having a plurality of types of execution units, the computer instructions are grouped in bundles, and each bundle includes a plurality of instructions and an associated index code. Template values are stored in a plurality of template registers, and each template value specifies types of execution units for a bundle of instructions and those instructions in a bundle that are executable in parallel. A dispatch logic circuit is coupled to the template registers and is responsive to an input bundle of instructions and associated index value. The dispatch logic circuit reads a code from a selected one of the plurality of template registers referenced by the index value and issues one or more selected instructions in the bundle to at least one execution unit of a selected type responsive to the code read from the selected one of the plurality of template registers.

Executing Conditional Branch Instructions In A Data Processor Having A Clustered Architecture

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US Patent:
7337306, Feb 26, 2008
Filed:
Dec 29, 2000
Appl. No.:
09/751410
Inventors:
Mark Owen Homewood - Winscombe, GB
Gary L. Vondran - San Carlos CA, US
Geoffrey M. Brown - Watertown MA, US
Paolo Faraboschi - Brighton MA, US
Assignee:
STMicroelectronics, Inc. - Carrollton TX
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 9/32
US Classification:
712234, 712 28
Abstract:
There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

System And Method For Reducing Power Consumption In A Data Processor Having A Clustered Architecture

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US Patent:
7779240, Aug 17, 2010
Filed:
Sep 14, 2007
Appl. No.:
11/900978
Inventors:
Mark Owen Homewood - Winscombe, GB
Gary L. Vondran - San Carlos CA, US
Geoffrey M. Brown - Watertown MA, US
Paolo Faraboschi - Brighton MA, US
Assignee:
STMicroelectronics, Inc. - Carrollton TX
Hewlett-Packard Company - Palo Alto
International Classification:
G06F 9/00
US Classification:
712234
Abstract:
There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Producing Marketing Items For A Marketing Campaign

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US Patent:
8090612, Jan 3, 2012
Filed:
Jul 19, 2005
Appl. No.:
11/184098
Inventors:
Hui Chao - San Jose CA, US
Menaka Indrani - Fremont CA, US
Gary Vondran - San Carlos CA, US
Xiaofan Lin - Sunnyvale CA, US
Parag M. Joshi - Los Gatos CA, US
Dirk M. Beyer - Walnut Creek CA, US
C. Brian Atkins - Mountain View CA, US
Pere Obrador - Mountain View CA, US
Alex Xin Zhang - San Jose CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06Q 30/00
US Classification:
705 729
Abstract:
Methods, machines, systems and machine-readable instructions for producing marketing items are described. In one aspect, a user is prompted to specify campaign parameters, including one or more campaign topics, defining a scope of the campaign. The user is prompted to specify for each of the one or more campaign topics a corresponding set of one or more attributes of intended recipients of the marketing campaign. The one or more specified campaign topics are associated to respective sets of targeted recipients selected from a database of records of potential recipients based on mappings of the respective sets of recipient attributes to the campaign topics and the specified campaign parameters defining the scope of the marketing campaign. For each of the targeted recipients, a respective marketing item containing a respective set of one or more contents matched to the campaign topic associated to the targeted recipient is composed.

Method And Apparatus For Efficient Cache Mapping Of Compressed Vliw Instructions

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US Patent:
20020091892, Jul 11, 2002
Filed:
Jan 9, 2001
Appl. No.:
09/757558
Inventors:
Gary Vondran - San Carlos CA, US
International Classification:
G06F012/08
US Classification:
711/003000, 712/024000, 711/125000
Abstract:
A method and apparatus for efficient cache mapping of compressed Very Long Instruction Word (VLIW) instructions. In the present invention, efficient cache mapping of compressed variable length cache lines is performed by decompressing a sequence of compressed instructions to obtain decompressed cache lines and storing the decompressed cache lines in the same sequence in the cache memory. The present invention decouples the program counter based cache mapping from the memory address. In this way, a fixed increment cache pointer and variable size compressed cache line can be achieved, and, in doing so, decompressed cache lines fit nicely within the cache, in sequential order, while variable length compressed cache lines can be directly accessed without the use of a translation table.

Cache Coherent Split Transaction Memory Bus Architecture And Protocol For A Multi Processor Chip Device

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US Patent:
20030023794, Jan 30, 2003
Filed:
Jul 26, 2001
Appl. No.:
09/916598
Inventors:
Padmanabha Venkitakrishnan - Sunnyvale CA, US
Shankar Venkataraman - Danville CA, US
Paul Keltcher - Sunnyvale CA, US
Stuart Siu - Castro Valley CA, US
Stephen Richardson - Los Altos CA, US
Gary Vondran - San Carlos CA, US
International Classification:
G06F013/42
US Classification:
710/105000
Abstract:
A cache coherent multiple processor integrated circuit. The circuit includes a plurality of processor units. The processor units are each provided with a cache unit. An embedded RAM unit is included for storing instructions and data for the processor units. A cache coherent bus is coupled to the processor units and the embedded RAM unit. The bus is configured to provide cache coherent snooping commands to enable the processor units to ensure cache coherency between their respective cache units and the embedded RAM unit. The multiple processor integrated circuit can further include an input output unit coupled to the bus to provide input and output transactions for the processor units. The bus is configured to provide split transactions for the processor units coupled to the bus, providing better bandwidth utilization of the bus. The bus can be configured to transfer an entire cache line for the cache units of the processor units in a single clock cycle, wherein the bus is 256 bits wide. The embedded RAM unit can be implemented as an embedded DRAM core. The multiple processor integrated circuit is configured to support a symmetric multiprocessing method for the plurality of processor units. The processor units can be configured to provide read data via the bus, as in a case of a read request by one processor when the read data is stored within a respective cache unit of another processor.

Wireless Trusted Point Of Access To A Computer Network

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US Patent:
20030083062, May 1, 2003
Filed:
Oct 31, 2001
Appl. No.:
09/999395
Inventors:
Emiliano Bartolome - Palo Alto CA, US
Gary Vondran - San Carlos CA, US
International Classification:
H04Q007/20
US Classification:
455/426000, 455/003050, 455/410000
Abstract:
A communication system includes a computer network that includes a plurality of interconnected computer devices. The communication system further includes at least one network device capable of communicating with one or more mobile wireless devices. The network device is part of the computer network and is capable of communicating with a mobile wireless device without the mobile wireless device being a member of the computer network.
Gary L Vondran from San Francisco, CA, age ~86 Get Report