Frank Huebinger

7651942, Jan 26, 2010

Aug 15, 2005

11/203883

Frank Huebinger - Poughkeepsie NY, US
Michael Beck - Poughkeepsie NY, US

Infineon Technologies AG - Munich

H01L 21/4763

438639, 438638, 438702, 257E21579, 257E2158

A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.

7687862, Mar 30, 2010

May 13, 2008

12/120055

Frank Huebinger - Poughkeepsie NY, US
Richard Lindsay - Beacon NY, US

Infineon Technologies AG - Neubiberg

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119
H01L 27/10
H01L 27/12
H01L 31/0392
H01L 23/62

257369, 257331, 257338, 257341, 257342, 257350, 257351, 257357, 257358, 257359, 257371, 257401, 257E21623, 257E21637, 257E21553

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

7723818, May 25, 2010

May 22, 2007

11/805232

Armin Tilke - Dresden, DE
Frank Huebinger - Poughkeepsie NY, US
Hermann Wendt - Poughkeepsie NY, US

Infineon Technologies AG - Neubiberg

H01L 29/00
H01L 21/76

257520, 438437

Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.

7883987, Feb 8, 2011

Apr 16, 2010

12/762172

Armin Tilke - Dresden, DE
Frank Huebinger - Poughkeepsie NY, US
Hermann Wendt - Poughkeepsie NY, US

Infineon Technologies AG - Neubiberg

H01L 21/76
H01L 29/00

438437, 257520

Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.

8003458, Aug 23, 2011

Feb 23, 2010

12/710911

Frank Huebinger - Poughkeepsie NY, US
Richard Lindsay - Beacon NY, US

Infineon Technologies AG - Neubiberg

H01L 21/8238

438221, 438283, 438429, 438480, 438584, 438587, 257E21633, 257E21642

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

20080108219, May 8, 2008

Nov 3, 2006

11/592427

Frank Huebinger - Poughkeepsie NY, US
Moosung Chae - Poughkeepsie NY, US
Armin Tilke - Dresden, DE
Hermann Wendt - Poughkeepsie NY, US

H01L 21/4763

438618

An integrated circuit interconnect structure includes a conductive line, a first barrier layer disposed on a bottom surface of conductive line, a second barrier layer disposed on the top surface of the conductive line, and an interlevel dielectric surrounding the conductive line.

20090014807, Jan 15, 2009

Jul 13, 2007

11/777290

Teck Jung TANG - Johor Bahru, MY
Dae Kwon Kang - Suwon-Si, KR
Tae Hoon Lee - Suwon-Si, KR
Scott D. Allen - Ledgewood NJ, US
Fang Chen - Singapore, SG
Frank Huebinger - Poughkeepsie NY, US
Jun Jung Kim - Paju-Si, KR
Jae Eun Park - Fishkill NY, US

Chartered Semiconductor Manufacturing, Ltd. - Singapore
Samsung Electronics Co., Ltd - Suwon-Si
International Business Machines Corporation - New York
Infineon Technologies AG - Munich

H01L 29/94
H01L 21/8238

257369, 438218, 438229, 257E29345, 257E21632

Dual stress liners for CMOS applications are provided. The dual stress liners can be formed from silicon nitride having a first portion for inducing a first stress and a second portion for inducing a second stress. An interface between the first and second stress portions is self-aligned and co-planar. To produce a co-planar self-aligned interface, polishing, for example, mechanical chemical polishing is used.

20090283853, Nov 19, 2009

May 13, 2008

12/120021

Frank Huebinger - Poughkeepsie NY, US

H01L 29/00
H01L 21/82
H01L 21/479

257529, 438132, 438467, 257E29001, 257E21602, 257E21498

Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link.