Search

Frank R Dropps

from Annandale, MN
Age ~63
Get Report
Also known as:
Frank Raymond Dropps, Frank E Dropps, Kourtney Dropps, Kirstin Dropps
Phone and address:
10997 Lawrence Ave NW, Annandale, MN 55302
(320) 274-1074
Related to:
Tim J Klinger, 67Kwinton DroppsNicolejean Petty, 45Nicole Petty, 45James PettyPaula Petty
Connected to:
David J Dropsey, 46Michael P Dropsey, 33Patrick W Dropsey, 68Moshe S Dror, 47Shlomit Dror, 43Chancey L Drorbaugh, 46Dustin D Drorbaugh, 45Gideon Drori, 68Matan Drori, 48Helen M Drosak, 74

Frank Dropps Phones & Addresses

  • 10997 Lawrence Ave NW, Annandale, MN 55302 (320) 274-1074
  • Mora, MN
  • 17222 81St Ave N, Osseo, MN 55311 (763) 420-7400
  • Maple Grove, MN
  • Minneapolis, MN
  • Eau Claire, WI
  • Wright, MN
  • Chippewa Falls, WI
  • 17222 81St Ave N, Maple Grove, MN 55311

Work

Company: Seagate technology Sep 2013 to Dec 2014 Position: Ssd system architecture and advanced development

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of Minnesota 1995 to 2006 Specialities: Electrical Engineering, Computer Science, Physics, Philosophy

Skills

Asic • System Architecture • Hardware Architecture • Verilog • Embedded Systems • Testing • Simulations • Hardware • Cmos • Microprocessors • Soc • Analog • Fibre Channel • Pcb Design • Low Power Design • Debugging • Fpga • Ethernet • Logic Design • Firmware • Pcie • Technical Leadership • Application Specific Integrated Circuits • Computer Hardware • Device Drivers • System Design • Digital Electronics • Tcl • Integration • Switches • Rtl Design • Patents • Network Switch Asics • Asic Architecture • Fcoe • Systemverilog • Scsi • I2C • Iscsi • System on A Chip • Field Programmable Gate Arrays

Industries

Computer Hardware

Resumes

Resumes

Frank Dropps Photo 1

President And Founder

View page
Location:
10997 Lawrence Ave northwest, Annandale, MN 55302
Industry:
Computer Hardware
Work:
Seagate Technology Sep 2013 - Dec 2014
Ssd System Architecture and Advanced Development
Qlogic May 1999 - Oct 2013
Engineer Consultant
Ddr Corp. May 1999 - Oct 2013
President and Founder
Angeion Corporation 1995 - 1999
Lead Hardware Design Engineer
Cray Research 1991 - 1995
Logic Design Engineer Iii
Education:
University of Minnesota 1995 - 2006
Doctorates, Doctor of Philosophy, Electrical Engineering, Computer Science, Physics, Philosophy University of Minnesota 1988 - 1990
Masters, Electrical Engineering Minnesota State University, Mankato 1980 - 1984
Bachelors, Electronics Engineering
Skills:
Asic
System Architecture
Hardware Architecture
Verilog
Embedded Systems
Testing
Simulations
Hardware
Cmos
Microprocessors
Soc
Analog
Fibre Channel
Pcb Design
Low Power Design
Debugging
Fpga
Ethernet
Logic Design
Firmware
Pcie
Technical Leadership
Application Specific Integrated Circuits
Computer Hardware
Device Drivers
System Design
Digital Electronics
Tcl
Integration
Switches
Rtl Design
Patents
Network Switch Asics
Asic Architecture
Fcoe
Systemverilog
Scsi
I2C
Iscsi
System on A Chip
Field Programmable Gate Arrays

Publications

Us Patents

Deterministic And Jitter-Free Dual-Chamber Cardiac Pacemaker

View page
US Patent:
6366810, Apr 2, 2002
Filed:
Sep 14, 1999
Appl. No.:
09/395432
Inventors:
Sharon Johnson - Lino Lakes MN
Frank Dropps - Maple Grove MN
James Marcotte - Arden Hills MN
Assignee:
Angeion Corporation - Minneapolis MN
International Classification:
A61N 118
US Classification:
607 9
Abstract:
A deterministic and jitter-free dual chamber brady pacemaker utilizes both a programmed microprocessor and a hardware state machine, both of which are coupled to a real time clock (RTC), random access memory (RAM) and a common escape interval timer. Time of occurrence (TOC) data representative of the time and nature of atrial and ventricular sensed events and pacing events is stored in the RAM. Escape interval periods are timed by the escape interval timer. The microprocessor is operable in both an active mode and an inactive mode without interrupts. In response to the receipt of wakeup commands, the microprocessor operates in the active mode and uses the TOC data from the RAM to reset the escape interval timer to a desired next event interval. The hardware state machine uses the common escape interval timer for timing timeout events and atrial and ventricular sensed events such that pacing pulses are delivered in a determinate manner.

Current Monitor For An Implantable Medical Device

View page
US Patent:
6898463, May 24, 2005
Filed:
Mar 19, 2002
Appl. No.:
10/102076
Inventors:
Frank R. Dropps - Maple Grove MN, US
Dennis A. Brumwell - Bloomington MN, US
Assignee:
Medtronic, Inc. - Minneapolis MN
International Classification:
A61N001/37
US Classification:
607 27, 607 34, 607 63
Abstract:
A method and an apparatus for performing a device component failure analysis in an implantable medical device using current consumption data. A current consumption signal relating to current consumption in an implantable medical device is generated. The current consumption signal is then processed. A defect of a component in the implantable medical device is assessed in response to the processing of the current consumption signal and appropriate action is taken, such as selecting alternate therapies, generating an alert signal, and turning off circuits corresponding to the assessed defect.

Apparatus And Method For Transmitting An Electrical Signal In An Implantable Medical Device

View page
US Patent:
7027862, Apr 11, 2006
Filed:
Jul 25, 2002
Appl. No.:
10/202920
Inventors:
Roger Dahl - Andover MN, US
Frank Dropps - Maple Grove MN, US
Randy Nelson - Pine Springs MN, US
Mark Stockburger - Inver Grove Heights MN, US
Assignee:
Medtronic, Inc. - Minneapolis MN
International Classification:
A61N 1/36
A61N 1/39
US Classification:
607 4, 607 5, 607 9
Abstract:
A method and device for transmitting a signal in an implantable medical device that includes a control unit and a first electrode and a second electrode positioned along a lead body. A connector block is positioned along an upper portion of a housing portion of the control unit, and a connector is positioned at a proximal portion of the lead body and is insertable within the connector block. A third electrode having a conductive element is positioned along the control unit in close proximity adjacent to the connector. The control unit transmits a signal between the first electrode and the second electrode and determines an alternate transmission path of the signal between the third electrode and one or both of the first electrode and the second electrode in response to the signal not being effectively transmitted between the first electrode and the second electrode.

Hardware-Enforced Loop-Level Hard Zoning For Fibre Channel Switch Fabric

View page
US Patent:
7248580, Jul 24, 2007
Filed:
Dec 5, 2002
Appl. No.:
10/310653
Inventors:
William R. George - Minneapolis MN, US
Frank R. Dropps - Maple Grove MN, US
Assignee:
QLogic Switch Products, Inc. - Eden Prairie MN
International Classification:
H04L 12/56
US Classification:
370389, 707 9, 709223
Abstract:
Hardware-enforced zoning is provided in Fibre Channel switches to protect against breaching of assigned zones in a switch network which can occur with software-based zoning techniques. The invention provides logic for performing a hardware-based validation of the Source ID S_ID of frames both at the point where the frame enters the Fibre Channel fabric, and at the point where the frame leaves the fabric. The S_ID is verified against an inclusion list or table of allowable S_IDs, which can be unique for each fabric port. The invention provides a way to increase the range of sources an inclusion table can express, by implementing wild cards, on an entry-by entry basis. If the S_ID is valid, it will enter the fabric and route normally. If invalid, the frame will not be routed but will be disposed of by the fabric according to FC rules. This prevents incorrect S_IDs from breaching the table-driven zoning at the point where frames exit the fabric, to prevent unauthorized access to devices connected to the switch network.

Integrated Fibre Channel Fabric Controller

View page
US Patent:
7404020, Jul 22, 2008
Filed:
Jul 20, 2004
Appl. No.:
10/894529
Inventors:
Frank R. Dropps - Maple Grove MN, US
William J. Gustafson - Apple Valley MN, US
Leonard W. Haseman - Eagan MN, US
Assignee:
QLOGIC, Corporation - Aliso Viejo CA
International Classification:
G06F 13/38
US Classification:
710 71, 710 8, 710306, 370258
Abstract:
A fibre channel switch element with an integrated fabric controller on a single chip is provided. The fabric controller including a processor module that can control various switch element functions; a serlizer/de-serializer for converting parallel data to serial data for transmission; an on-chip peripheral bus that allows communication between plural components and the processor module; a processor local bus and an interrupt controller that provides interrupts to the processor module. The integrated fabric controller also includes a flash controller and an external memory controller; an Ethernet controller; a Universal Asynchronous Receiver Transmitter (“UART”) module that performs serial to parallel conversion and vice-versa; an IC module that performs serial to parallel and parallel to serial conversion; a general-purpose input/output interface; a real time clock module; an interrupt controller that can receive interrupts inputs from both internal and external sources; and a bridge to an internal PCI bus.

Programmable Pseudo Virtual Lanes For Fibre Channel Systems

View page
US Patent:
7406092, Jul 29, 2008
Filed:
Jul 20, 2004
Appl. No.:
10/894597
Inventors:
Frank R. Dropps - Maple Grove MN, US
Edward C. Ross - Edina MN, US
Assignee:
QLOGIC, Corporation - Aliso Viejo CA
International Classification:
H04J 3/16
US Classification:
370437
Abstract:
A method and switch element for assigning priority to pseudo virtual lanes (“PVL”) using a fibre channel switch element is provided. The method includes, assigning received R_RDYs based on a PVL distribution scheme; and determining traffic congestion on a PVL if there is no credit available to transfer frames from the PVL. A minimum bandwidth feature is enabled to avoid lower priority PVLs from getting no credit for transmitting frames; and distributing credit and R_RDYs based on frame age bits, wherein a lower priority PVL gets credit if a frame is waiting in the PVL for a longer duration compared to a higher priority PVL. The switch element includes, a PVL module having credit counters for plural PVLs; and a timer that monitors frame traffic for each PVL lane. If a PVL gets congested, then a state machine adjusts priority of R_RDY distribution scheme of other PVLs to transmit frames.

Method And System For Transferring Data Directly Between Storage Devices In A Storage Area Network

View page
US Patent:
7411958, Aug 12, 2008
Filed:
Oct 1, 2004
Appl. No.:
10/956717
Inventors:
Frank R. Dropps - Maple Grove MN, US
Kevin M. Wurzer - Edina MN, US
Assignee:
QLOGIC, Corporation - Aliso Viejo CA
International Classification:
H04L 12/28
US Classification:
370392, 370419, 710100
Abstract:
A method and system for performing a copy operation between storage devices coupled to a Fiber Channel switch element is provided. The Fiber Channel switch element receives a user command to copy data from a source storage device to a destination storage device and controls the copying operation. The Fiber Channel switch acts as a SCSI initiator and initiates a write operation for the destination storage device and initiates a read operation for the source storage device; and uses an alias cache for intercepting messages between the destination and source storage devices. A RX_ID mapping cache is used to substitute a RX_ID so that that a Fiber Channel write target appears to the source storage device as the destination storage device, and to the destination storage device a Fiber Channel read target appears to be the source storage device.

Method And System For Keeping A Fibre Channel Arbitrated Loop Open During Frame Gaps

View page
US Patent:
7420982, Sep 2, 2008
Filed:
Jul 20, 2004
Appl. No.:
10/894491
Inventors:
Frank R. Dropps - Maple Grove MN, US
Ernest G. Kohlwey - Eagan MN, US
Gary M. Papenfuss - St. Paul MN, US
Assignee:
QLogic, Corporation - Aliso Viejo CA
International Classification:
H04L 12/56
US Classification:
370424, 370528
Abstract:
A method and system for keeping an arbitrated loop open during a frame gap using a fiber channel switch element is provided. The switch element includes a port control module having a receive and transmit segment, wherein the transmit segment activates a timer whose value determines a duration during which the arbitrated loop remains open; determines if a last frame from a sequence of frames from a source port has been transmitted; modifies the timer value if a higher priority frame for transmission is unavailable; and keeps the arbitrated loop open until the timer reaches a certain value. If a higher priority frame is available for transmission before the timer value is modified then the higher priority frame is transmitted and the timer value is re-initialized.
Control profile
Frank R Dropps from Annandale, MN, age ~63 Get Report