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Francois Ducaroir

from Santa Clara, CA
Age ~62
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Also known as:
Francois Dell Olio, Ducaroir Francois
Phone and address:
672 Park Ct, Santa Clara, CA 95050
(408) 425-2185
Related to:
Olio Michela Dell, 63
Connected to:
Phyllis M Ducary, 92Alain Ducas, 53Ashley M Ducas, 33Eric P Ducas, 43Jamie L Ducas, 43Joan Ducas, 89Alyssa J Ducasse, 29Howard V Ducasse, 36Ignacio Ducasse, 63Jenny M Ducasse, 71

Francois Ducaroir Phones & Addresses

  • 672 Park Ct, Santa Clara, CA 95050 (408) 425-2185
  • San Francisco, CA

Resumes

Resumes

Francois Ducaroir Photo 1

Principal Engineer

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Location:
672 Park Ct, Santa Clara, CA 95050
Industry:
Semiconductors
Work:
Xilinx since 2008
Principal Engineer
LSI Jan 2007 - 2008
Director of Engineering
LSI Logic 2003 - 2006
Director of Engineering
LSI Logic 1995 - 2003
Engineering Manager
LSI Logic 1991 - 1994
Design Engineer
Skills:
Semiconductors
Soc
Asic
Ic
Mixed Signal
Engineering
Semiconductor Industry
Serdes
Processors
Francois Ducaroir Photo 2

Francois Ducaroir

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Location:
United States

Publications

Us Patents

Serial Data Transceiver Including Elements Which Facilitate Functional Testing Requiring Access To Only The Serial Data Ports, And An Associated Test Method

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US Patent:
6341142, Jan 22, 2002
Filed:
Dec 16, 1997
Appl. No.:
08/991715
Inventors:
Francois Ducaroir - Santa Clara CA
Karl S. Nakamura - Palo Alto CA
Michael O. Jenkins - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04L 516
US Classification:
375219, 375224
Abstract:
A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal. When the test signal is asserted, the second router routes the parallel output data produced by the receiver to the first router, and the first router routes the parallel output data produced by the receiver to the transmitter.

Serial Data Transmitter With Bit Doubling

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US Patent:
7342977, Mar 11, 2008
Filed:
Nov 26, 2002
Appl. No.:
10/304922
Inventors:
Michael O. Jenkins - San Jose CA, US
Brett D. Hardy - Chaska MN, US
Francois Ducaroir - Santa Clara CA, US
Michael Okronglis - Bloomington MN, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04L 27/00
H04L 12/50
H03M 9/00
US Classification:
375295, 341100, 341101, 370366
Abstract:
A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of adjacent bits to form an expanded data word. Each of the expanded data words is serialized to form a serial data word stream, which is transmitted.

Loop-Back Test System And Method

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US Patent:
57871140, Jul 28, 1998
Filed:
Jan 17, 1996
Appl. No.:
8/586174
Inventors:
Krishnan Ramamurthy - Santa Clara CA
Rong Pan - Aberdeen NJ
Francois Ducaroir - Santa Clara CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04B 144
US Classification:
375221
Abstract:
A loop back test system and method for providing local fault detection within the core or macrocell of an integrated I/O interface device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The loop back of input test data from the transmitters output directly to the receiver's input permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the loop back of serialized, alignment pattern encoded parallel data from the output stage of the I/O transmitter to the receiver's input stage permits identifying faults occurring within the integrated I/O transceiver macrocell. The loop back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Enhanced Receiving Chip For A Computer Monitor

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US Patent:
60852577, Jul 4, 2000
Filed:
Oct 16, 1997
Appl. No.:
8/951896
Inventors:
Francois Ducaroir - Santa Clara CA
Karl S. Nakamura - Palo Alto CA
Michael O. Jenkins - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04N 714
US Classification:
710 1
Abstract:
An improved transceiver that is tightly integrated into an enhanced receiving chip for a computer monitor. The transceiver includes a receiver having a first input port for receiving serialized data, a first output port for transmitting deserialized data to the transceiver, and a second input port adapted for receiving feedback data forwarded from a sensor to an audio and video control unit. The serialized data comprises video, audio and control data. The transceiver further comprises a receiver operably coupled between the first input port and the first output port, as well as a timing generator coupled to recover a clock signal from the serialized data and to synchronize the deserialized data from the recovered clock. The transceiver also includes a transmitter with a third input port for receiving parallel data and a second output port for transmitting a serial data stream. The parallel data are received by the third input port concurrently with the serialized data being received by the first input port.

Wrap-Back Test System And Method

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US Patent:
59563702, Sep 21, 1999
Filed:
Jan 17, 1996
Appl. No.:
8/586173
Inventors:
Francois Ducaroir - Santa Clara CA
Rong Pan - Stanford CA
Krishnan Ramamurthy - Santa Clara CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04B 144
US Classification:
375221
Abstract:
A wrap back test system and method for providing local fault detection within a section of an integrated I/O interface core device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The wrap back of input test data, prior to reformatting for transmission, to the receiver's data alignment stage permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the wrap back of alignment pattern encoded parallel data, prior to serialization, to the receiver's data alignment stage permits identifying faults in just this portion of the I/O transceiver. The wrap back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

High Speed Serial Line Transceivers Integrated Into A Cache Controller To Support Coherent Memory Transactions In A Loosely Coupled Network

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US Patent:
63305917, Dec 11, 2001
Filed:
Mar 9, 1998
Appl. No.:
9/036897
Inventors:
Francois Ducaroir - Santa Clara CA
Karl S. Nakamura - Palo Alto CA
Michael O. Jenkins - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1338
US Classification:
709213
Abstract:
One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent.

High Speed Phase Locked Loop Test Method And Means

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US Patent:
57810389, Jul 14, 1998
Filed:
Feb 5, 1996
Appl. No.:
8/597896
Inventors:
Krishnan Ramamurthy - Santa Clara CA
Rong Pan - Aberdeen NJ
Ross MacTaggart - Eden Prarie MN
Francois Ducaroir - Santa Clara CA
Assignee:
LSI Logic Corporation
International Classification:
H03K 522
US Classification:
327 23
Abstract:
A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).

Apparatus And Method For Testing The Ability Of A Pair Of Serial Data Transceivers To Transmit Serial Data At One Frequency And To Receive Serial Data At Another Frequency

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US Patent:
62086219, Mar 27, 2001
Filed:
Dec 16, 1997
Appl. No.:
8/991906
Inventors:
Francois Ducaroir - Santa Clara CA
Karl S. Nakamura - Palo Alto CA
Michael O. Jenkins - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04L12/26
US Classification:
370241
Abstract:
An apparatus and method are presented for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency. A serial communication device of the present invention includes a first and second serial data transceivers and a multiplexer formed upon a monolithic semiconductor substrate. Each serial data transceiver includes a receiver and a transmitter which transmits serial data in response to a clock signal. The second serial data transceiver is coupled to receive a reference clock signal. The multiplexer facilitates testing, and is coupled to the first serial data transceiver. The multiplexer receives the reference clock signal, a test clock signal, and a test signal, and provides either the reference clock signal or the test clock signal to the first transceiver dependent upon the test signal. The reference and test clock signals have different frequencies. The multiplexer provides the reference clock signal to the first transceiver when the test signal is deasserted, and provides the test clock signal to the first transceiver when the test signal is asserted.
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Francois Ducaroir from Santa Clara, CA, age ~62 Get Report