Search

Farzad E Etemadi

from Laguna Niguel, CA
Age ~56
Get Report
Also known as:
Farzad F Etemadi
Phone and address:
29 Mallorca, Laguna Beach, CA 92677
(949) 218-9904
Related to:
James R Lacy, 67Shannon LacyOmid Etemadi, 58James S Jamie, 43Masoud Etemadi
Connected to:
Bijan M Etemadi, 70Helen Etemadi, 57Lidia X Etemadi, 33Maryam Etemadi, 67Mina Etemadi, 71Niloufar Etemadi, 38Michelle L Eten, 59Stuart Etengoff, 64Wayne E Eternicka, 56Ever Eternity, 47

Farzad Etemadi Phones & Addresses

  • 29 Mallorca, Laguna Niguel, CA 92677 (949) 218-9904
  • 4412 City Lights Dr, Aliso Viejo, CA 92656 (949) 581-5642
  • 43 Woodswallow Ln, Aliso Viejo, CA 92656 (949) 581-5642
  • Laguna Beach, CA
  • 5124 Verano Pl, Irvine, CA 92612 (949) 509-0868
  • 322 Knollglen, Irvine, CA 92614 (949) 653-7241
  • Alviso, CA
  • Orange, CA

Work

Company: Broadcom Aug 2007 Address: Irvine, CA Position: Principal scientist, mobile and wireless group

Education

Degree: Doctor of Philosophy (Ph.D.) School / High School: University of California, Irvine 2002 to 2007 Specialities: Electrical Engineering and Computer Science

Skills

Lte • Analog • Modeling • Signal • Tds • Simulation • 2G • Dsp • Receivers

Languages

English • Farsi

Industries

Telecommunications

Resumes

Resumes

Farzad Etemadi Photo 1

Phy Systems And Algorithm Engineer

View page
Location:
Laguna Niguel, CA
Industry:
Telecommunications
Work:
Broadcom - Irvine, CA since Aug 2007
Principal Scientist, Mobile and Wireless Group
Broadcom - Irvine, CA Feb 1998 - Jul 2002
Design Engineer, Broadband Communications Group
UCI Advanced Computer Architecture Lab - Irvine, CA Jan 1996 - Dec 1997
Research and Teaching Assistant
Standard Microsystems Corporation - Irvine, CA Jun 1997 - Sep 1997
Engineering Intern
Matn Electric Power Research Center 1992 - 1995
Research Engineer
Education:
University of California, Irvine 2002 - 2007
Doctor of Philosophy (Ph.D.), Electrical Engineering and Computer Science University of California, Irvine 1996 - 1997
Master of Science (MSc), Electrical and Computer Engineering Sharif University of Technology 1986 - 1991
Bachelor of Science (BSc), Electrical Engineering
Skills:
Lte
Analog
Modeling
Signal
Tds
Simulation
2G
Dsp
Receivers
Languages:
English
Farsi

Publications

Us Patents

Lock Detector For Phase Locked Loops

View page
US Patent:
6580328, Jun 17, 2003
Filed:
Feb 27, 2001
Appl. No.:
09/794310
Inventors:
Loke Kun Tan - Laguna Niguel CA
Farzad Etemadi - Irvine CA
Denny Yuen - Torrance CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03L 7093
US Classification:
331 17, 331 23, 331 25, 331DIG 2, 375340, 375376
Abstract:
A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

Lock Detector For Phase Locked Loops

View page
US Patent:
6803828, Oct 12, 2004
Filed:
May 9, 2003
Appl. No.:
10/435446
Inventors:
Loke Kun Tan - Laguna Niguel CA
Farzad Etemadi - Irvine CA
Denny Yuen - Torrance CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03L 7095
US Classification:
331 17, 331 18, 331DIG 2, 331 23, 375340, 375376
Abstract:
A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

Spur Mitigation For Radio Frequency Receivers Utilizing A Free-Running Crystal

View page
US Patent:
8542784, Sep 24, 2013
Filed:
Jun 22, 2011
Appl. No.:
13/166507
Inventors:
Farzad Etemadi - Laguna Niguel CA, US
Massoud Kahrizi - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 27/06
US Classification:
375344, 375319
Abstract:
Embodiments of a receiver for using a first oscillator signal provided by a crystal resonator to support multiple, different functionalities are provided. The receiver comprises a phase-locked loop (PLL) configured to provide a second oscillator signal based on the first oscillator signal provided by the crystal resonator; a first mixer configured to mix a received signal received over a first input path with the second oscillator signal received over a second input path to provide a first frequency-shifted signal; and an automatic frequency controller (AFC) configured to estimate a frequency offset of the second oscillator signal and adjust the PLL to compensate for the frequency offset. The receiver further can include solutions for mitigating potential sources of noise caused by the frequency of the first oscillator signal not being compensated for by the AFC.

Long-Term Drift Mitigation For Radio Frequency Receivers Utilizing A Free-Running Crystal

View page
US Patent:
8594251, Nov 26, 2013
Filed:
Jun 22, 2011
Appl. No.:
13/166519
Inventors:
Farzad Etemadi - Laguna Niguel CA, US
Massoud Kahrizi - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 27/06
US Classification:
375344, 375346, 375347, 375326, 375327, 375147
Abstract:
Embodiments of a receiver for using a first oscillator signal provided by a crystal resonator to support multiple, different functionalities are provided. The receiver comprises a phase-locked loop (PLL) configured to provide a second oscillator signal based on the first oscillator signal provided by the crystal resonator; a first mixer configured to mix a received signal received over a first input path with the second oscillator signal received over a second input path to provide a first frequency-shifted signal; and an automatic frequency controller (AFC) configured to estimate a frequency offset of the second oscillator signal and adjust the PLL to compensate for the frequency offset. The receiver further can include solutions for mitigating potential sources of noise caused by the frequency of the first oscillator signal not being compensated for by the AFC.

Lock Detector For Phase Locked Loops

View page
US Patent:
20040232951, Nov 25, 2004
Filed:
Jun 30, 2004
Appl. No.:
10/880934
Inventors:
Loke Tan - Laguna Niguel CA, US
Farzad Etemadi - Aliso Viejo CA, US
Denny Yuen - Torrance CA, US
Assignee:
Broadcom Corporation
International Classification:
H03B021/00
H04K001/00
US Classification:
327/105000
Abstract:
A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

Iq Gain Imbalance Correction For Receivers Employing Sigma-Delta Analog To Digital Conversion

View page
US Patent:
20120263262, Oct 18, 2012
Filed:
Apr 14, 2011
Appl. No.:
13/087057
Inventors:
Farzad ETEMADI - Laguna Niguel CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 27/08
US Classification:
375345
Abstract:
Embodiments of an apparatus for improving a gain imbalance between an in-phase and quadrature component recovered by a receiver are provided. The apparatus includes a first transition counter configured to count a number of bit transitions in a first sequence of one-bit values provided by a first sigma-delta modulator based on the in-phase component, and a second transition counter configured to count a number of bit transitions in a second sequence of one-bit values provided by a second sigma-delta modulator based on the quadrature component. The apparatus further includes a gain monitor configured to: (1) determine a first and second power level, proportional to a power of the in-phase and quadrature components respectively, using the number of bit transitions in the first and second sequences, and (2) adjust a gain of one of the in-phase and quadrature components based on a ratio between the first and second power levels.

Radio Transceiver With Im2 Mitigation

View page
US Patent:
20130155911, Jun 20, 2013
Filed:
Dec 16, 2011
Appl. No.:
13/328794
Inventors:
Masoud Kahrizi - Irvine CA, US
Nooshin Vakilian - Irvine CA, US
Farzad Etemadi - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 7/00
H04B 1/46
US Classification:
370277, 455 79
Abstract:
A structure and method to reduce second order intermodulation (IM2) of a receiver in a transceiver is provided. Specifically, the output of a detector in a transmit power control loop is utilized to calculate IM2 and the value is subtracted from a receive path to mitigate IM2 in a wireless communication devices. Alternatively, the detector can be placed in one or more receive paths to include receiver front-end passband variation.

Lock Detector For Phase Locked Loops

View page
US Patent:
62117424, Apr 3, 2001
Filed:
Nov 3, 1999
Appl. No.:
9/433811
Inventors:
Loke Kun Tan - Laguna Niguel CA
Farzad Etemadi - Irvine CA
Denny Yuen - Torrance CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03L 7095
US Classification:
331 25
Abstract:
A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.
Control profile
Farzad E Etemadi from Laguna Niguel, CA, age ~56 Get Report