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Eugene G Dierschke

from Dallas, TX
Age ~82

Eugene Dierschke Phones & Addresses

  • 6709 Leameadow Dr, Dallas, TX 75248 (972) 233-8780
  • Rowena, TX
  • Winters, TX
  • 6709 Leameadow Dr, Dallas, TX 75248 (281) 345-9653

Work

Position: Machine Operators, Assemblers, and Inspectors Occupations

Education

Degree: Bachelor's degree or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
Eugene G. Dierschke
General Partner
DIERSCHKE FAMILY LIMITED PARTNERSHIP
Business Services
6709 Leameadow Dr, Dallas, TX 75248
Eugene G. Dierschke
Chief Scientist
TAOS INC
Semiconductors · Mfg Semiconductors/Related Devices Whol Electronic Parts/Equipment
1001 Klein SUITE 300, Plano, TX 75074
5556 Tennyson Pkwy, Plano, TX 75024
(972) 673-0759

Publications

Us Patents

Optical Sensor Array With Zone-Programmable Gain And Offset

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US Patent:
6353401, Mar 5, 2002
Filed:
Jun 15, 1999
Appl. No.:
09/333850
Inventors:
Cecil J. Aswell - Organgevale CA
Eugene G. Dierschke - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03M 106
US Classification:
341118, 341120, 341139
Abstract:
An optical sensor array with zone-programmable gain and offset prior to A/D conversion for reducing quantization noise. The circuit comprises a register file which contains digital words for controlling gain and offset according to multi-pixel zones.

Temperature And Process Compensated Ldmos Drain-Source Voltage

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US Patent:
6384643, May 7, 2002
Filed:
Nov 22, 2000
Appl. No.:
09/721393
Inventors:
William E. Grose - Plano TX
Eugene G. Dierschke - Dallas TX
Jingwei Xu - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03K 1714
US Classification:
327112, 327333, 327362, 327378, 327513
Abstract:
Driver circuitry ( ) is disclosed, incorporating feedback circuitry ( ) inter-coupled with reference circuitry ( ) to equalize the voltage level of an output ( ) with a reference voltage source ( ) in the reference circuitry; where the driver circuitry comprises a first transistor ( ) having a first terminal coupled to a voltage source ( ), a second terminal coupled to an input ( ), and a third terminal coupled to a resistor ( ), a second transistor ( ) having a first terminal coupled to ground ( ), a second terminal coupled to an input ( ), and a third terminal coupled to a resistor ( ), a third transistor ( ) having a first terminal coupled to the output, a second terminal ( ) coupled jointly to the resistors, and a third terminal coupled to ground, and a resistor ( ) coupling the output to a voltage source ( ).

Addressing And Communication For Multiple-Chip Optical Sensor Arrays

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US Patent:
6553437, Apr 22, 2003
Filed:
Jun 15, 1999
Appl. No.:
09/334205
Inventors:
Cecil J. Aswell - Organgevale CA
Eugene G. Dierschke - Dallas TX
Carlo S. Strippoli - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1310
US Classification:
710 36, 710 3, 710 8, 710 9, 710 10, 710 41
Abstract:
A technique for serially controlling an array of optical sensor chips over a pair of signal lines. After broadcasting an initializing reset command to all chips over serial lines, a determine-address command is broadcast to commence unique address determination. On subsequent clock signals, each chip locks its address into an on-board register. Following this process, each chip can be addressed individually. Subsequently, when each array chip is directed to read data out, the data is output to a single common bus line to the controller. Alternatively, individual chip outputs may be connected directly to the controller, or the outputs of odd and even chip pairs may be tied together for broadcast readout of all odd chips or all even chips.

Method And Apparatus For Optical Detector With Special Discrimination

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US Patent:
6596981, Jul 22, 2003
Filed:
Jan 14, 2002
Appl. No.:
10/047484
Inventors:
Cecil Aswell - Orangevale CA
Eugene G. Dierschke - Dallas TX
Lester L. Hodson - McKinney TX
Assignee:
Texas Advanced Optoelectronic Solutions, Inc. - Plano TX
International Classification:
H01L 3100
US Classification:
2502141, 257435, 257440
Abstract:
A monolithic optical detector for determining spectral content of an incident light includes at least a first and second well in a substrate, the second well formed proximate the first well. The first well is configured to be exposed to incident light and for generating a first photocurrent as a function of the incident light. The second well is configured to be shielded from the incident light and for generating a second photocurrent as a function of the incident light. Lastly, a processing and control unit, responsive to the first and second photocurrents, determines an indication of spectral content of the incident light. A method and device parameter controller are also disclosed.

Mismatch-Independent Reset Sensing For Cmos Area Array Sensors

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US Patent:
6618083, Sep 9, 2003
Filed:
Dec 30, 1998
Appl. No.:
09/223698
Inventors:
Zhiliang Julian Chen - Plano TX
Eugene G. Dierschke - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04N 314
US Classification:
348243, 348308
Abstract:
Two methods for suppressing the fixed pattern noise effects of a pixel reset switch by ensuring that the reset NMOS device operates in its linear region. The first approach uses a separate reset switch supply voltage, V , set to at least one threshold voltage below the sensing switch supply voltage, V. The second approach uses a charge pump and level shifter to push the reset gate voltage at least one threshold voltage higher than a supply voltage common to both the reset and sense transistors.

Fast Frame Readout Architecture For Array Sensors With Integrated Correlated Double Sampling System

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US Patent:
6697108, Feb 24, 2004
Filed:
Dec 30, 1998
Appl. No.:
09/223166
Inventors:
Zhiliang Julian Chen - Plano TX
Eugene G. Dierschke - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04N 5217
US Classification:
348241, 348308
Abstract:
A MOS architecture for reading rows of pixels in an area array imager. After initial setup, individual pixels are read one row at a time using one clock pulse per pixel.

Digital Imaging Control With Selective Intensity Resolution Enhancement

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US Patent:
6788340, Sep 7, 2004
Filed:
Dec 30, 1999
Appl. No.:
09/475901
Inventors:
Zhiliang Julian Chen - Plano TX
Eugene G. Dierschke - Dallas TX
Steven Derek Clynes - Allen TX
Anli Liu - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04N 5235
US Classification:
3482291, 348243
Abstract:
Image enhancement is automatically achieved by calibrating the reference voltage and gain of a differential amplifier and the integration interval so as to provide an input to a differential analog to digital converter (ADC) that utilizes the full dynamic range of the ADC. When used with a CMOS array, the imaging logic can be fabricated on a single chip with the array using combinational logic for fast, inexpensive calibration. Another advantageous feature is the ability to expand a desired portion of the luminance spectrum of the image in order to increase the digital resolution of the resulting image for that portion of the spectrum of interest.

Charge-Coupled Amplifier And Converter With Matched Offsets

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US Patent:
6943721, Sep 13, 2005
Filed:
Jun 15, 1999
Appl. No.:
09/333849
Inventors:
Cecil J. Aswell - Organgevale CA, US
Eugene G. Dierschke - Dallas TX, US
John Hull Berlien Jr. - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03M001/12
US Classification:
341172, 341155, 341150
Abstract:
An linear optical sensor charged-coupled topology using single-stage inverting charge-coupled amplifier driving an analog-to-digital converter which uses the converter full-scale reference as a precharge level. Since an offset in the range of 100–200 mV is introduced in the charge amplifier, a corresponding offset is also introduced into the ADC to allow the amplifier to more quickly drive the amplifier output to a low level. The converter offset is proportional to the converter reference to ensure that it is controlled and tracks the reference.
Eugene G Dierschke from Dallas, TX, age ~82 Get Report