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Emre X Alptekin

from Los Gatos, CA
Age ~42
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Also known as:
Emre Alppekin, Emra N
Connected to:
Alfonso D Alpuerto, 58Erica C Alpuerto, 29Mohammed A Alqadi, 31Ahmad M Alqahtani, 86Ayed Q Alqahtani, 48Faisal Alqahtani, 36Mohamed S Alqahtani, 68Othman M Alqahtani, 36Ali Alqaisi, 33Iyad A Alqam, 40

Emre Alptekin Phones & Addresses

  • Los Gatos, CA
  • 503 Chinook Ln, San Jose, CA 95123
  • Ballston Spa, NY
  • Wappingers Falls, NY
  • Fishkill, NY
  • Raleigh, NC
  • Cary, NC

Publications

Us Patents

Selective Threshold Voltage Implants For Long Channel Devices

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US Patent:
8298895, Oct 30, 2012
Filed:
Oct 31, 2011
Appl. No.:
13/285282
Inventors:
Emre Alptekin - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/336
US Classification:
438276, 438289, 438525, 257E21443
Abstract:
In a replacement metal gate process flow, sacrificial gates are exposed and removed subsequent to the formation of source and drain regions for various transistor devices. Sidewalls formed adjacent to the sacrificial gates remain. By using an angled implant such that, for a short-channel device, the remaining sidewalls shadow and protect the exposed short-channel region, a designer may adjust the threshold voltage on long-channel devices without affecting the threshold voltage of the short-channel device.

Method Of Forming Silicide Contacts Of Different Shapes Selectively On Regions Of A Semiconductor Device

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US Patent:
8415250, Apr 9, 2013
Filed:
Apr 29, 2011
Appl. No.:
13/097459
Inventors:
Emre Alptekin - Wappingers Falls NY, US
Viraj Yashawant Sardesai - Poughkeepsie NY, US
Cung Do Tran - Newburgh NY, US
Jian Yu - Danbury CT, US
Reinaldo Ariel Vega - Wappingers Falls NY, US
Rajasekhar Venigalla - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/417
US Classification:
438666, 257E29116, 257410, 257773, 438300
Abstract:
A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

Method To Form Uniform Silicide By Selective Implantation

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US Patent:
8492275, Jul 23, 2013
Filed:
Jul 20, 2011
Appl. No.:
13/186519
Inventors:
Emre Alptekin - Wappingers Falls NY, US
Viraj Y. Sardesai - Poughkeepsie NY, US
Cung D. Tran - Newburgh NY, US
Bin Yang - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
GlobalFoundries, Inc. - Grand Cayman
International Classification:
H01L 21/44
US Classification:
438682, 438630, 257E21438, 257E21439
Abstract:
Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

Multi-Stage Silicidation Process

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US Patent:
8603915, Dec 10, 2013
Filed:
Nov 28, 2011
Appl. No.:
13/305122
Inventors:
Emre Alptekin - Wappingers Falls NY, US
Ahmet S. Ozcan - Pleasantville NY, US
Viraj Y. Sardesai - Poughkeepsie NY, US
Cung D. Tran - Newburgh NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/44
US Classification:
438674, 438682, 438664
Abstract:
A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.

Two-Step Silicide Formation

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US Patent:
20120223372, Sep 6, 2012
Filed:
Mar 3, 2011
Appl. No.:
13/039678
Inventors:
Emre Alptekin - Wappingers Falls NY, US
Sameer Hemchand Jain - Beacon NY, US
Reinaldo Ariel Vega - Wappingers Falls NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 29/772
H01L 21/28
US Classification:
257288, 438660, 257E21158, 257E29242
Abstract:
An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.

Mosfet Integrated Circuit With Uniformly Thin Silicide Layer And Methods For Its Manufacture

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US Patent:
20130069124, Mar 21, 2013
Filed:
Sep 20, 2011
Appl. No.:
13/237732
Inventors:
Bin Yang - San Carlos CA, US
Christian Lavoie - Pleasantville NY, US
Emre Alptekin - Wappingers Falls NY, US
Ahmet S. Ozcan - Pleasantville NY, US
Cung D. Tran - Newburgh NY, US
Mark Raymond - Schenectady NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
GLOBALFOUNDRIES INC. - Grand Cayman
International Classification:
H01L 29/78
H01L 21/20
US Classification:
257288, 438655, 257E21129, 257E29255
Abstract:
An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

Contact Structures For Semiconductor Transistors

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US Patent:
20130154026, Jun 20, 2013
Filed:
Dec 20, 2011
Appl. No.:
13/330817
Inventors:
Emre Alptekin - Wappingers Falls NY, US
Reinaldo Vega - Wappingers Falls NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 27/088
H01L 21/768
US Classification:
257384, 438655, 257E2706, 257E21585
Abstract:
Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.

Method For Cleaning Semiconductor Substrate

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US Patent:
20130273737, Oct 17, 2013
Filed:
Apr 17, 2012
Appl. No.:
13/448497
Inventors:
Emre Alptekin - Wappingers Falls NY, US
Ahmet Serkan Ozcan - Pleasantville NY, US
Viraj Yashawant Sardesai - Poughkeepsie NY, US
Cung Do Tran - Newburgh NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 21/02
US Classification:
438664, 438694
Abstract:
Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.
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Emre X Alptekin from Los Gatos, CA, age ~42 Get Report