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Edward R Prack

from Phoenix, AZ
Age ~67
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Also known as:
Edward M Prack, Ed M Prack, Charlotte Hammersmith
Related to:
Mark S Prack, 65Christina F Cipolletti, 56Melissa S Jackson, 44Nettie PrackMelissa D Prack, 44Maureen A Prack, 89Annette M Prack, 61Brenda K Prack, 65Michelle R Prack, 41
Connected to:
Barbara J Prack, 67Christopher D Prack, 63Elyse H Prack, 70Megan P Pracko, 35David J Pracon, 68Alberto A Prada, 61Alirio Prada, 77Angelo R Prada, 57Anne C Prada, 45

Edward Prack Phones & Addresses

  • Phoenix, AZ
  • 655 Ridge St, Willard, OH 44890
  • 102 Indian Bend Dr, Austin, TX 78734
  • Lakeway, TX
  • Norwalk, OH
  • Maricopa, AZ
  • Sleepy Hollow, IL
  • Chandler, AZ

Business Records

Name / Title
Company / Classification
Phones & Addresses
Edward R Prack
Director
MASIP LLC
3055 E Bighorn Ave, Phoenix, AZ 85048
Edward M Prack
K & H DRUG OF NORWALK, INC
Norwalk, OH
Edward M Prack
K & H DRUG OF WILLARD, INC
Willard, OH

Publications

Us Patents

Method Of Manufacturing A Semiconductor Component And Polyimide Etchant Therefor

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US Patent:
6664200, Dec 16, 2003
Filed:
Apr 28, 2000
Appl. No.:
09/560974
Inventors:
Edward R. Prack - Austin TX, 78734
Frank W. Fischer - Mesa AZ, 85210
Treliant Fang - Chandler AZ, 85226
International Classification:
H01L 2131
US Classification:
438780, 438781, 148DIG 75
Abstract:
A method of manufacturing a semiconductor component having a layer ( ) comprised of polyimide includes using an etchant that is at least partially composed of aminopropanediol to etch the layer comprised of polyimide. The etchant can also include a solvent, a diluent, and water.

Circuit Device With At Least Partial Packaging And Method For Forming

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US Patent:
6838776, Jan 4, 2005
Filed:
Apr 18, 2003
Appl. No.:
10/418763
Inventors:
George R. Leal - Cedar Park TX, US
Edward R. Prack - Austin TX, US
Robert J. Wenzel - Austin TX, US
Brian D. Sawyer - Mesa AZ, US
David G. Wontor - Austin TX, US
Marc Alan Mangrum - Manchaca TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 2940
H01L 2328
US Classification:
257783, 257723, 257787, 438106
Abstract:
In one embodiment, circuit device () is placed within an opening of a conductive layer () which is then partially encapsulated with an encapsulant () so that the active surface of the circuit device () is coplanar with the conductive layer (). In this embodiment, at least a portion of the conductive layer () may be used as a reference voltage plane (e. g. a ground plane). In one embodiment, circuit device () is placed on a conductive layer () such that an active surface of circuit device () is between conductive layer () and an opposite surface of circuit device (). In this embodiment, conductive layer () has at least one opening () to expose the active surface of circuit device (). The encapsulant () may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

Semiconductor Power Device With Shear Stress Compensation

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US Patent:
6888246, May 3, 2005
Filed:
May 29, 2003
Appl. No.:
10/447457
Inventors:
Lei L. Mercado - Gilbert AZ, US
Vijay Sarihan - Paradise Valley AZ, US
Young Sir Chung - Chandler AZ, US
James Jen-Ho Wang - Phoenix AZ, US
Edward R. Prack - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L023/48
H01L023/52
US Classification:
257751, 257750, 257762
Abstract:
In accordance with one embodiment, a stress buffer () is formed between a power metal structure () and passivation layer (). The stress buffer () reduces the effects of stress imparted upon the passivation layer () by the power metal structure (). In accordance with an alternative embodiment, a power metal structure (A) is partitioned into segments (), whereby electrical continuity is maintained between the segments () by remaining portions of a seed layer () and adhesion/barrier layer (). The individual segments () impart a lower peak stress than a comparably sized continuous power metal structure ().

Circuit Device With At Least Partial Packaging, Exposed Active Surface And A Voltage Reference Plane

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US Patent:
6921975, Jul 26, 2005
Filed:
Apr 18, 2003
Appl. No.:
10/418790
Inventors:
George R. Leal - Cedar Park TX, US
Edward R. Prack - Austin TX, US
Robert J. Wenzel - Austin TX, US
Brian D. Sawyer - Mesa AZ, US
David G. Wontor - Austin TX, US
Marc Alan Mangrum - Manchaca TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L023/538
H01L023/48
US Classification:
257723, 257686, 257685, 257777, 257684, 257796, 257712, 257713, 257691, 257698
Abstract:
A circuit device () is placed within an opening of a conductive layer () which is then partially encapsulated with an encapsulant () so that the active surface of the circuit device () is coplanar with the conductive layer (). At least a portion of the conductive layer () may be used as a reference voltage plane (e. g. a ground plane). Additionally, a circuit device () may be placed on a conductive layer () such that an active surface of circuit device () is between conductive layer () and an opposite surface of circuit device (). The conductive layer () has at least one opening () to expose the active surface of circuit device (). The encapsulant () may be electrically conductive or electrically non-conductive.

Forming Carbon Nanotube Capacitors

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US Patent:
7428138, Sep 23, 2008
Filed:
Oct 6, 2005
Appl. No.:
11/244540
Inventors:
Larry E. Mosley - Santa Clara CA, US
James G. Maveety - San Jose CA, US
Edward R. Prack - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01G 9/04
US Classification:
361508, 361502, 361504, 361512, 361311, 361313
Abstract:
A capacitor may be formed of carbon nanotubes. Carbon nanotubes, grown on substrates, may be formed in a desired pattern. The pattern may be defined by placing catalyst in appropriate locations for carbon nanotube growth from a substrate. Then, intermeshing arrays of carbon nanotubes may be formed by juxtaposing the carbon nanotubes formed on opposed substrates. In some embodiments, the carbon nanotubes may be covered by a dielectric which may be adhered by functionalizing the carbon nanotubes.

Adhesive System For Supporting Thin Silicon Wafer

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US Patent:
7462551, Dec 9, 2008
Filed:
Sep 30, 2005
Appl. No.:
11/241499
Inventors:
Sudhakar N. Kulkarni - Chandler AZ, US
Leonel R. Arana - Phoeniz AZ, US
Edward R. Prack - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/30
H01L 21/46
US Classification:
438455, 257E21567, 438458
Abstract:
In some embodiments, an adhesive system for supporting thin silicon wafer is presented. In this regard, a method is introduced to bond a silicon wafer to a translucent carrier through the use of an adhesive. Other embodiments are also disclosed and claimed.

Article Having Metal Impregnated Within Carbon Nanotube Array

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US Patent:
7545030, Jun 9, 2009
Filed:
Dec 30, 2005
Appl. No.:
11/323205
Inventors:
Gregory M. Chrysler - Chandler AZ, US
Thomas S. Dory - Gilbert AZ, US
James G. Maveety - San Jose CA, US
Edward Prack - Phoenix AZ, US
Unnikrishnan Vadakkanmaruveedu - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/12
US Classification:
257686, 257E23112, 977742, 977748
Abstract:
A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Process Of Making Carbon Nanotube Array That Includes Impregnating The Carbon Nanotube Array With Metal

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US Patent:
7964447, Jun 21, 2011
Filed:
May 8, 2009
Appl. No.:
12/387871
Inventors:
Gregory M. Chrysler - Chandler AZ, US
Thomas S. Dory - Gilbert AZ, US
James G. Maveety - San Jose CA, US
Edward Prack - Phoenix AZ, US
Unnikrishnan Vadakkanmaruveedu - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/58
US Classification:
438109, 438122, 257E21505, 977847
Abstract:
A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
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Edward R Prack from Phoenix, AZ, age ~67 Get Report