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Donald Soltis Phones & Addresses
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6903 White Snow Ct, Timnath, CO 80547 (970) 227-5094
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126 Cuna Way, Red Feather Lakes, CO 80545
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4414 Rosegate Ct, Fort Collins, CO 80526
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Windsor, CO
Work
Company:
United states
Position:
Bay view
Publications
Us Patents
Superword Memory-Access Instructions For Data Processor
View pageUS Patent:
7680990, Mar 16, 2010
Filed:
May 30, 2003
Appl. No.:
10/449442
Inventors:
Donald C. Soltis - Fort Collins CO, US
Dale C. Morris - Steamboat Springs CO, US
Dean Ahmad Mulla - Saratoga CA, US
Achmed Rumi Zahir - Menlo Park CA, US
Amy Lynn O'Donnell - Ann Arbor MI, US
Allan Douglas Knies - San Francisco CA, US
Dale C. Morris - Steamboat Springs CO, US
Dean Ahmad Mulla - Saratoga CA, US
Achmed Rumi Zahir - Menlo Park CA, US
Amy Lynn O'Donnell - Ann Arbor MI, US
Allan Douglas Knies - San Francisco CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
G06F 13/00
G06F 13/28
US Classification:
711154
Abstract:
Atomic sixteen-byte memory accesses are provided in a 64-bit system in which eight of the bytes are stored in a 64-bit general-purpose register and eight of the bytes are stored in a 64-bit special-purpose register. A 16-byte load instruction transfers the low eight bytes to an explicitly specified general-purpose register, while the high eight bytes are transferred to the special-purpose register. Likewise, a 16-byte store instruction transfers data from a general-purpose register and the special-purpose register. Also provided is an 8-byte compare conditioning a 16-byte exchange semaphore instruction that can be used to accelerate algorithms that use multiple processors to simultaneously read and update large databases.
System And Method For Coalescing Data Utilized To Detect Data Hazards
View pageUS Patent:
20030051121, Mar 13, 2003
Filed:
Oct 28, 2002
Appl. No.:
10/282183
Inventors:
Ronny Arnold - Ft Collins CO, US
Donald Soltis - Fort Collins CO, US
Donald Soltis - Fort Collins CO, US
International Classification:
G06F009/30
US Classification:
712/216000
Abstract:
The present invention generally relates to a processing system and method for coalescing instruction data to efficiently detect data hazards between instructions of a computer program. In architecture, the system of the present invention utilizes a plurality of pipelines, coalescing circuitry, and hazard detection circuitry. The plurality of pipelines is configured to process instructions of a computer program, and the coalescing circuitry is configured to receive, from the pipelines, a plurality of register identifiers identifying a plurality of registers. The coalescing circuitry is configured to coalesce said register identifiers thereby generating a coalesced register identifier identifying each of said plurality of registers. The hazard detection circuitry is configured to receive the coalesced register identifier and to perform a comparison of the coalesced register identifier with other information received from the pipelines. The hazard detection circuitry is further configured to detect a data hazard based on the comparison.
Method And System For Detecting Dropped Micro-Packets
View pageUS Patent:
20030110422, Jun 12, 2003
Filed:
Dec 12, 2001
Appl. No.:
10/021170
Inventors:
Samuel Naffziger - Fort Collins CO, US
Donald Soltis - Fort collins CO, US
Donald Soltis - Fort collins CO, US
International Classification:
H04B001/74
US Classification:
714/048000
Abstract:
A system and a method of providing error detection and correction of transmission of multiple flits between sending and receiving agents connected together in a network or computer interconnect environment is disclosed that comprises embedding a sequence identifier in each flit prior to transmission, sending each flit to a connected receiving agent, examining the sequence identifiers of each flit being received and requesting the sending agent to resend a flit if the sequence identifier for that flit is determined to be incorrect. In a preferred embodiment of the present invention, the sequence identifier is embedded in the control portion of the flit and comprises a sequence number that is incremented or otherwise changed in a predictable manner, so that the order of flits being received is predicted. If the sequence number for a flit is different that expected, the receiving agent requests that it be resent.
Stacked Register Aliasing In Data Hazard Detection To Reduce Circuit
View pageUS Patent:
20030154363, Aug 14, 2003
Filed:
Feb 11, 2002
Appl. No.:
10/074061
Inventors:
Donald Soltis - Fort Collins CO, US
Rohit Bhatia - Fort Collins CO, US
Ronny Arnold - Fort Collins CO, US
Rohit Bhatia - Fort Collins CO, US
Ronny Arnold - Fort Collins CO, US
International Classification:
G06F009/30
US Classification:
712/217000
Abstract:
The invention recasts the virtual register file frame calls to alias hazard detection in the hazard detect logic of the physical register file. By way of example, mapping to the stacked registers may be aliased with three sets of 32 registers rows, from 32 to 127, for data hazard calculations to decrease size implementation with minor performance decrease. The invention sacrifices occasional hazard detections—resulting in occasional pipeline stalls as a loss of processor performance—in order to remove the row-by-row dependencies on physical register size. The invention thus reduces the logic requirements associated with the “height” and “width” of the register file: “height” corresponds to the number of registers (e.g., 128), and “width” corresponds to the pipeline stages. The physical register size of the invention is effectively greater than what may be accessed by software at any time; there is no longer a one-to-one correspondence between the virtual and physical register files. In addition, there is no longer a one-to-one correspondence between physical registers and register identifiers for data hazard purposes. Accordingly, more physical registers may be added without a corresponding increase in the hazard detect and bypass logic. If a data hazard exists, an occasional pipeline stall may occur that would not have occurred by incorporating a one-to-one mapping between the register identifiers and physical register files. The physical and decode logic is simplified for the multiple rows of the register file, thereby reducing physical size and power requirements for the EPIC processor.
Register Renaming To Reduce Bypass And Increase Apparent Physical Register Size
View pageUS Patent:
20030163672, Aug 28, 2003
Filed:
Feb 11, 2002
Appl. No.:
10/074098
Inventors:
Eric Fetzer - Longmont CO, US
Donald Soltis - Fort Collins CO, US
Stephen Undy - Fort Collins CO, US
Donald Soltis - Fort Collins CO, US
Stephen Undy - Fort Collins CO, US
International Classification:
G06F009/30
US Classification:
712/218000
Abstract:
The invention provides a processor architecture that bypasses data hazards. The architecture has an array of pipelines and a register file. Each of the pipelines includes an array of execution units. The register file has a first section of n registers (e.g., 128 registers) and a second section of m registers (e.g., 16 registers). A write mux couples speculative data from the execution units to the second set of m registers and non-speculative data from a write-back stage of the execution units to the first section of n registers. A read mux couples the speculative data from the second set of m registers to the execution units to bypass data hazards within the execution units. The register file preferably includes column decode logic for each of the registers in the second section of m registers to architect speculative data without moving data. The decode logic first decodes, and then selects, an age of the producer of the speculative state; the newest producer enables the decode.
Apparatus And Methods For Interfacing With Cache Memory
View pageUS Patent:
20030167379, Sep 4, 2003
Filed:
Mar 1, 2002
Appl. No.:
10/086494
Inventors:
Donald Soltis - Fort Collins CO, US
International Classification:
G11C005/00
US Classification:
711/119000, 710/317000, 711/003000
Abstract:
A processing system includes a processor, a main memory, a cache and a crossbar interface between the processor and the cache. In a multiprocessing system, a plurality of main memory address ranges can be mapped to a plurality of caches, and a plurality of caches can be mapped to a plurality of processors. Thus a significant degree of flexibility is provided in configuring a processing system.
Core Parallel Execution With Different Optimization Characteristics To Decrease Dynamic Execution Path
View pageUS Patent:
20030167389, Sep 4, 2003
Filed:
Mar 4, 2002
Appl. No.:
10/091084
Inventors:
Donald Soltis - Fort Collins CO, US
Eric Delano - Fort Collins CO, US
Eric Delano - Fort Collins CO, US
International Classification:
G06F009/00
US Classification:
712/220000
Abstract:
The invention provides a processor with two or more parallel instruction paths for processing instructions. The instruction paths may be implemented with a plurality of cores on a common die. Instructions of the invention are preferably processed within a bundle of two or more instructions of a common program thread; and each of the instruction paths preferably forms a cluster to process bundled instructions. Each of the instruction paths has an array of pipelined execution units. Initially, two or more of the parallel instruction paths processes the same program thread (one or more bundles) through the execution units, but with different optimization characteristics set for each path. Assessment logic monitors the processing of the initial program thread through the execution units and selects the heuristics defining which path is in the lead. The other instruction paths are then reallocated, or synchronized, with the optimization characteristics of the lead instruction path, or with similarly optimized characteristics, to process other bundles of the program thread; preferably, the lead path continues processing of the initial thread without being disturbed. For other program threads, the process may repeat in processing like bundles through multiple instruction paths to identify the preferred heuristics; and then synchronizing the multiple instruction paths to the optimized characteristics to improve per thread performance.
System And Method For Dynamic Processor Core And Cache Partitioning On Large-Scale Multithreaded, Multiprocessor Integrated Circuits
View pageUS Patent:
20030172234, Sep 11, 2003
Filed:
Mar 6, 2002
Appl. No.:
10/092645
Inventors:
Donald Soltis - Fort Collins CO, US
International Classification:
G06F012/08
US Classification:
711/122000
Abstract:
A processor integrated circuit capable of executing more than one instruction stream has two or more processors. Each processor accesses instructions and data through a cache controller. There are also multiple blocks of cache memory. Some blocks of cache memory may optionally be directly attached to particular cache controllers. The cache controllers access at least some of the multiple blocks of cache memory through a high speed interconnect, at least one of the these blocks being dynamically allocable to more than one cache controller. A resource allocation controller determines which cache memory controller has access to the at least one dynamically allocable cache memory block. In an embodiment the cache controllers and cache memory blocks heretofore described are associated with second level cache, each processor accesses the second level cache controllers upon missing in a first level cache of fixed size. The associated method provides for billing of processor time according to the amount of cache allocated to processors associated with a particular partition of a machine containing at least one processor integrated circuit having allocable cache.