Search

Dmitri B Strukov

from Goleta, CA
Age ~47
Get Report
Also known as:
Dimitri Strukov, Ditri Strukov
Phone and address:
4057 Foothill Rd APT F, Santa Barbara, CA 93110
Related to:
Yuri Gennady Strukov, 52
Connected to:
Borislav B Strulev, 47Angelise Strull, 41Cynthia S Strull, 71Lynnette E Struloeff, 61Eric A Strulowitz, 64Michelle Strulovic, 37Zalmen Strulovic, 54Deborah L Strum, 61Howard I Strum, 100Jennifer J Strum, 55

Dmitri Strukov Phones & Addresses

  • 4057 Foothill Rd APT F, Santa Barbara, CA 93110
  • Goleta, CA
  • Mountain View, CA
  • Menlo Park, CA
  • 21 Brightwaters Dr, Sound Beach, NY 11789 (631) 744-2742
  • Port Jefferson, NY
  • East Setauket, NY
  • San Francisco, CA
  • Stony Brook, NY

Work

Company: Uc santa barbara Position: Professor at ucsb

Skills

Cooking • Birdwatching • Movingwaterwatching

Languages

English

Industries

Higher Education

Resumes

Resumes

Dmitri Strukov Photo 1

Professor At Ucsb

View page
Location:
2208 Pacific Coast Dr, Goleta, CA
Industry:
Higher Education
Work:
Uc Santa Barbara
Professor at Ucsb
Skills:
Cooking
Birdwatching
Movingwaterwatching
Languages:
English

Publications

Us Patents

Testing A Nonvolatile Circuit Element Having Multiple Intermediate States

View page
US Patent:
8310252, Nov 13, 2012
Filed:
Oct 26, 2009
Appl. No.:
12/605441
Inventors:
Matthew D Pickett - San Francisco CA, US
Dmitri Borisovich Strukov - Mountain View CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G01R 31/3187
G01R 31/02
US Classification:
32475014, 3247503, 32475601, 365148, 327524
Abstract:
A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.

Three Dimensional Multilayer Circuit

View page
US Patent:
8373440, Feb 12, 2013
Filed:
Apr 6, 2009
Appl. No.:
13/256233
Inventors:
Dmitri Borisovich Strukov - Menlo Park CA, US
R. Stanley Williams - Portola Valley CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H03K 19/173
US Classification:
326 38, 326103
Abstract:
A three dimensional multilayer circuit includes a via array made up of a set of first vias and a set of second vias and an area distributed CMOS layer configured to selectively address said first vias and said second vias. At least two crossbar arrays overlay the area distributed CMOS layer. These crossbar arrays include a plurality of intersecting crossbar segments and programmable crosspoint devices which are interposed between the intersecting crossbar segments. The vias are connected to the crossbar segments such that each programmable crosspoint devices can be uniquely accessed using a first via and a second via.

Dense Nanoscale Logic Circuitry

View page
US Patent:
8390323, Mar 5, 2013
Filed:
Apr 30, 2009
Appl. No.:
13/256234
Inventors:
Dmitri Borisovich Strukov - Menlo Park CA, US
Philip J. Kuekes - Menlo Park CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H03K 19/177
US Classification:
326 38, 326 41
Abstract:
One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.

Memcapacitive Devices

View page
US Patent:
8493138, Jul 23, 2013
Filed:
Aug 26, 2009
Appl. No.:
12/548124
Inventors:
John Paul Strachan - Milibrae CA, US
Gilberto Ribeiro - Menlo Park CA, US
Dmitri Strukov - Mountain View CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G11C 11/00
US Classification:
327554, 257532, 365129
Abstract:
A memcapacitive device includes a first electrode having a first end and a second end and a second electrode. The device has a memcapacitive matrix interposed between the first electrode and the second electrode. The memcapacitive matrix has a non-linear capacitance with respect to a voltage across the first electrode and the second electrode. The memcapacitive matrix is configured to alter a signal applied on the first end by at least one of a) changing at least one of a rise-time and a fall-time of the signal and b) delaying the transmission of the signal based on the application of a programming voltage across the first electrode and the second electrode.

Memristive Transistor Memory

View page
US Patent:
8507968, Aug 13, 2013
Filed:
Jan 30, 2009
Appl. No.:
13/142581
Inventors:
Dmitri B. Strukov - Menlo Park CA, US
Philip J. Kuekes - Menlo Park CA, US
Duncan Stewart - Ottawa, CA
Zhiyong Li - Redwood City CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H01L 29/76
H01L 21/336
US Classification:
257314, 438288
Abstract:
A memory device () includes a semiconductor wire including a source region (), a drain region (), and a channel region () between the source region () and the drain region (). A gate structure that overlies the channel region includes a memristive portion () and a conductive portion () overlying the memristive portion ().

Reconfigurable Multilayer Circuit

View page
US Patent:
8530880, Sep 10, 2013
Filed:
Jul 27, 2009
Appl. No.:
13/259168
Inventors:
Dmitri Borisovich Strukov - Mountain View CA, US
R. Stanley Williams - Portola Valley CA, US
Yevgeniy Eugene Shteyn - Cupertino CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H01L 29/06
H03K 19/177
H03K 25/00
H03K 19/173
US Classification:
257 5, 326 36, 326 41, 326 46
Abstract:
A reconfigurable multilayer circuit () includes a complimentary metal-oxide-semiconductor (CMOS) layer () having control circuitry, logic gates (), and at least two crossbar arrays () which overlie the CMOS layer (). The at least two crossbar arrays () are configured by the control circuitry and form reconfigurable interconnections between the logic gates () within the CMOS layer ().

Resistive Switches

View page
US Patent:
8570138, Oct 29, 2013
Filed:
Mar 3, 2010
Appl. No.:
13/387680
Inventors:
Jianhua Yang - Palo Alto CA, US
Dmitri Borisovich Strukov - Mountain View CA, US
Shih-Yuan Wang - Palo Alto CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H01C 7/10
US Classification:
338 20, 338 13
Abstract:
Resistive switches and related methods are provided. Such a resistive switch includes an active material in contact with opposite end electrodes. The active material defines electron traps that capture or release charges in accordance with applied switching voltages. Resistive switches are characterized by ON state and OFF state resistance curves. Resistance ratios of ten times or more are exhibited. The state of a resistive switch is determined using sensing voltages lesser then the switching threshold.

Memristive Switch Device

View page
US Patent:
8586959, Nov 19, 2013
Filed:
Apr 28, 2010
Appl. No.:
12/769557
Inventors:
Matthew D. Pickett - San Francisco CA, US
Jianhua Yang - Palo Alto CA, US
Dmitri Strukov - Mountain View CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H01L 47/00
US Classification:
257 4, 257 5, 257E29002
Abstract:
A memristive switch device can comprise a switch formed between a first electrode and a second electrode, where the switch includes a memristive layer and a select layer directly adjacent the memristive layer. The select layer blocks current to the memristive layer over a symmetric bipolar range of subthreshold voltages applied between the first and second electrodes.

Amazon

Hybrid CMOS/Memristor Nanoelectronics

View page
Author

Ming Liu,Dmitri Strukov,Garrett S. Rose, Wei Wang

Binding

Hardcover

Publisher

Springer Verlag

ISBN #

1461411610

EAN Code

9781461411611

ISBN #

1

Control profile
Dmitri B Strukov from Goleta, CA, age ~47 Get Report