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Dilip K Sampath

from Sunnyvale, CA
Age ~59
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Also known as:
Dilip Usha Sampath, Sampath Dipli, Sampath Dilip, Sampath P
Phone and address:
193 Sunset Ave, Sunnyvale, CA 94086
(408) 774-0110
Related to:
Sanjay Kumar Jain, 53Sampath M Seshadri, 58Usha Dilip, 56Sridhar Krishnan, 58
Connected to:
Anand Sampath, 47Asha Sampath, 71Chris V Sampath, 38Deepak M Sampathu, 47Geetha Sampathkumar, 58Gokul G Sampath, 32Kannan Sampath, 52Kaushik Sampath, 42Lavanya Sampathkumar, 45Nandhini Sampath, 37

Dilip Sampath Phones & Addresses

  • 193 Sunset Ave, Sunnyvale, CA 94086 (408) 774-0110
  • Milpitas, CA
  • San Jose, CA
  • Santa Clara, CA
  • Kearny, NJ

Resumes

Resumes

Dilip Sampath Photo 1

Sap Basis Consultant

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Location:
Sunnyvale, CA
Industry:
Computer Software
Work:
Praman Infotech Jun 2008 - Dec 2009
Assignment
Beyond It Solutions Jun 2008 - Dec 2009
Sap Basis Consultant
Education:
Sri Mallikarjuna Public School
Jawaharlal Nehru Technological University
Bachelors, Bachelor of Technology
Interests:
Playing Cricket
Watching Movies
Dilip Sampath Photo 2

Dilip Sampath

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Location:
San Francisco, CA
Industry:
Consumer Electronics
Work:
Nitto Innovation Sep 2014 - Sep 2015
Venture and New Business Consultant
Panasonic 2004 - 2013
Venture Partner
Multiple 2004 - 2013
Experience Related To Corporate Venturing : Advisory Board Member
Intel Corporation 1992 - 2002
Various
Vlsi Technology 1990 - 1992
Design Engineer
Education:
New Jersey Institute of Technology
Masters, Electronics Engineering, Electronics Annamalai University, Annamalainagar
Bachelors, Electronics Engineering, Electronics
Skills:
Strategy
Product Management
Strategic Partnerships
Start Ups
Business Strategy
New Business Development
Mergers and Acquisitions
Go To Market Strategy
Business Development
Entrepreneurship

Business Records

Name / Title
Company / Classification
Phones & Addresses
Dilip Sampath
Partner
Panasonic Technologies Inc
Electronic Research · Research and Development in the Physical, Engineering, and L
20300 Stevens Crk Blvd, Cupertino, CA 95014
(408) 861-3900, (408) 861-3990

Publications

Us Patents

Method And Apparatus For Transferring Data In Source-Synchronous Protocol And Transferring Signals In Common Clock Protocol In Multiple Agent Processing System

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US Patent:
6336159, Jan 1, 2002
Filed:
Jan 13, 1998
Appl. No.:
09/006322
Inventors:
Peter D. MacWilliams - Aloha OR
William S. Wu - Cupertino CA
Dilip K. Sampath - Sunnyvale CA
Bindi A. Prasad - Los Altos CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1342
US Classification:
710105, 713400
Abstract:
A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

Transmission Of Signals Synchronous To A Common Clock And Transmission Of Data Synchronous To Strobes In A Multiple Agent Processing System

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US Patent:
6598103, Jul 22, 2003
Filed:
Nov 6, 2001
Appl. No.:
09/991626
Inventors:
Peter D. MacWilliams - Aloha OR
William S. Wu - Cupertino CA
Dilip K. Sampath - Sunnyvale CA
Bindi A. Prasad - Los Altos CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1342
US Classification:
710105, 713400
Abstract:
A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

Method And Apparatus For Configuring The Pinout Of An Integrated Circuit

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US Patent:
61924318, Feb 20, 2001
Filed:
Dec 31, 1997
Appl. No.:
9/001550
Inventors:
Sanjay Dabral - Milpitas CA
Dilip K. Sampath - Sunnyvale CA
Christopher Cheng - Sunnyvale CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1000
US Classification:
710 62
Abstract:
A method and apparatus for configuring the pinout of an integrated circuit. An integrated circuit includes an input/output structure including an input/output port. The input/output structure communicates a first signal in a first configuration and a second signal in a second configuration. The first and second signals are parallel signals of a bus.

Computer System With A Semi-Differential Bus Signaling Scheme

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US Patent:
61544981, Nov 28, 2000
Filed:
Sep 26, 1997
Appl. No.:
8/938359
Inventors:
Sanjay Dabral - Milpitas CA
Dilip K. Sampath - Sunnyvale CA
Alper Ilkbahar - Santa Cruz CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04B 300
H04L 2300
H04L 2700
H03K 300
US Classification:
375257
Abstract:
A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.

Data-Pattern Induced Skew Reducer

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US Patent:
59535210, Sep 14, 1999
Filed:
Nov 3, 1997
Appl. No.:
8/962812
Inventors:
Sanjay Dabral - Milipitas CA
Dilip K. Sampath - Sunnyvale CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1338
US Classification:
395552
Abstract:
The amount of skew present in a signal delivered over a transmission line is reduced by identifying of the type of data pattern from which a bit of data is being sent and generating a corresponding delay in response to identification of the data pattern is described. The generated delay results in reducing the amount of skew present in the system. In a first configuration, the invention includes first-storage and second-storage mechanisms, a logic gate, first and second delay paths, and a mechanisms for generating an output terminal. The first-storage mechanism stores a first digital signal. The second-storage mechanism stores a second digital signal that occurs in a selected number of clock transitions after the first data signal. The two storage mechanisms are connected to a logic gate. The first storage mechanism is also connected to the first and second delay paths which delay signals sent to them.

Predriver Logic Circuit

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US Patent:
60436824, Mar 28, 2000
Filed:
Dec 23, 1997
Appl. No.:
8/997223
Inventors:
Sanjay Dabral - Milipitas CA
Dilip K. Sampath - Sunnyvale CA
Alper Ilkbahar - Santa Cruz CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 190175
H03K 19094
US Classification:
326 86
Abstract:
A buffer for enabling a signal to be applied to a bus. The buffer includes a first transistor coupled to a bus and a voltage supply. The logic buffer includes a first logic circuit which has an input coupled to receive a data signal and adapted to charge a terminal of the transistor at a first rate in response to a transition in the data signal. A second logic circuit charges the terminal at a faster rate during an initial transition period, until a first preselected condition is met. The buffer also includes a third logic circuit to charge the terminal at a second faster rate during a final transition period, after a second preselected condition is met. A method for controlling a voltage level of a signal applied to a terminal of a transistor includes charging the terminal at a fast rate until a first preselected condition is met. The terminal is then charged at a slower rate, until a second preselected condition is met, at which time the terminal is charged at a second fast rate, which is also greater than the slower rate.

Source Synchronous Interface Between Master And Slave Using A Deskew Latch

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US Patent:
62090720, Mar 27, 2001
Filed:
May 6, 1997
Appl. No.:
8/852438
Inventors:
Peter MacWilliams - Aloha OR
Bindi Prasad - Los Altos CA
Manoji Khare - Sunnyvale CA
Dilip Sampath - Sunnyvale CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F13/00;13/14
US Classification:
711167
Abstract:
A source synchronous interface between a master device and slave device is described. A master device having a plurality of deskew latches is coupled to a slave device via a bus. The master device communicates commands and first timing information to the slave device via the bus. In response, the slave device communicates data and second timing information to the master device via the bus. When data is communicated from the slave device to the master device, the data is stored in one of the plurality of deskew latches until accessed by the master device. The plurality of deskew latches ensure that the master device will always read valid data for the full range of skew of the first and second timing information.

Mechanism For Data Strobe Pre-Driving During Master Changeover On A Parallel Bus

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US Patent:
59648562, Oct 12, 1999
Filed:
Sep 30, 1997
Appl. No.:
8/940050
Inventors:
William S. Wu - Cupertino CA
Leonard Schultz - San Jose CA
Dilip K. Sampath - Sunnyvale CA
Muthurajan Jayakumar - Sunnyvale CA
Bindi A. Prasad - Los Altos CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1314
G06F 1300
G06F 104
US Classification:
710110
Abstract:
In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of: providing a first strobe signal and a second strobe signal for synchronizing said first and second data transfers with the bus clock; a pre-driving the first strobe signal before the first data transfer, the first strobe signal running at the bus clock rate during the first data transfer; and pre-driving one of the first and second strobe signals before the second data transfer, said one of the first and second strobe signals running at the bus clock rate during the second data transfer.
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Dilip K Sampath from Sunnyvale, CA, age ~59 Get Report