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Dilip M Risbud

from San Jose, CA
Age ~65
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Related to:
Amar Dilip Risbud, 30Rashmi D Risbud, 34Anuradha RisbudMuradha D Risbud
Connected to:
Joseph A Risby, 65Rodney L Risby, 57Juan V Riscajche, 44Denyelle L Riscassi, 54Armin Risch, 66Ashton W Risch, 47Bradley R Risch, 53Carl W Risch, 70Cynthia D Risch, 58Damian L Risch, 57

Dilip Risbud Phones & Addresses

  • 3325 Etoile Ct, San Jose, CA 95135 (408) 270-3750 (408) 270-9940
  • Sunnyvale, CA
  • Davis, CA
  • San Diego, CA

Resumes

Resumes

Dilip Risbud Photo 1

Gan Technologist - Power Semiconductors Product Architect At Nxp Semiconductors

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Position:
GaN Technologist - Power Semiconductors Product Architect at NXP Semiconductors
Location:
Hazel Grove, Greater Manchester, United Kingdom
Industry:
Semiconductors
Work:
NXP Semiconductors - Manchester, United Kingdom since Nov 2012
GaN Technologist - Power Semiconductors Product Architect
Integrated Device Technology Inc 2011 - 2012
Senior Director, Operations Development
National Semiconductor 2008 - 2011
* Member of Technical Staff - GaN Technology Applications Engineering
National Semiconductor 2003 - 2008
* Senior Engineering Manager & MTS - Product Engineering - Power Management; Corporate H/W Services
Marvell 2002 - 2003
* Director of Product Engineering - Data Communications and Wirless LAN Products
Education:
University of California, Santa Cruz 2008 - 2013
Ph.D., Electrical Engineering San Jose State University 1997 - 1999
MSEE, Electrical Engineering University of Phoenix 1995 - 1997
MBA, International Business Management Kansas State University 1981 - 1983
MS (Physics), Solid State Physics
Skills:
Characterization
Analog Intergrated Circuits
Engineering Management
Start-ups
Power Electronics
Operations Management
Semiconductor Process Technology
Compound Semiconductors
Analog
Semiconductors
IC
Mixed Signal
Interests:
Everything Physics, Analog Design, Cricket, Tennis, Biking, World Travel, Music, Teaching, Puzzles, Arguing against any organized religion, superstitions, blind faith!
Honor & Awards:
Research and Publications: • “An Effective Defect-Oriented BIST Architecture for High Speed Phase Locked Loops”, Kim, Soma, Risbud, January 2000, IEEE VLSI Test Symposium 2000, Montreal, Canada • Additional journal and conference publications in progress in the area of High Speed ADC design • Technical sponsor of University Collaborative Research at University of California - Santa Cruz and research reviewer at Stanford University • SRC Projects Mentor –University of Washington - Seattle, University of California – San Diego
Languages:
Hindi
Dilip Risbud Photo 2

Gan Power Technologist

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Location:
3325 Etoile Ct, San Jose, CA 95135
Industry:
Semiconductors
Work:
NXP Semiconductors - Manchester, United Kingdom since Nov 2012
GaN Technologist - Power Semiconductors Product Architect
Integrated Device Technology Inc 2011 - 2012
Senior Director, Operations Development
National Semiconductor 2008 - 2011
* Member of Technical Staff - GaN Technology Applications Engineering
National Semiconductor 2003 - 2008
* Senior Engineering Manager & MTS - Product Engineering - Power Management; Corporate H/W Services
Marvell 2002 - 2003
* Director of Product Engineering - Data Communications and Wirless LAN Products
Education:
University of California, Santa Cruz 2008 - 2013
Ph.D., Electrical Engineering San Jose State University 1997 - 1999
MSEE, Electrical Engineering University of Phoenix 1995 - 1997
MBA, International Business Management Kansas State University 1981 - 1983
MS (Physics), Solid State Physics
Skills:
Semiconductors
Ic
Mixed Signal
Analog
Yield
Engineering Management
Cmos
Asic
Analog Circuit Design
Failure Analysis
Characterization
Rf
Power Management
Circuit Design
Integrated Circuit Design
Start Ups
Power Electronics
Semiconductor Process Technology
Engineering
Operations Management
Bicmos
Pcb Design
Analog Intergrated Circuits
Compound Semiconductors
Interests:
Sweepstakes
Home Improvement
Reading
Gourmet Cooking
Sports
Golf
Home Decoration
Health
Teaching
Photograph
Children
Cooking
Electronics
Outdoors
Education
Cricket
Biking
Music
Science and Technology
Dogs
World Travel
Movies
Everything Physics
Kids
Puzzles
Poverty Alleviation
Analog Design
Boating
Investing
Tennis
Languages:
English
Hindi
Dilip Risbud Photo 3

Dilip Risbud

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Publications

Us Patents

Methods Of Manufacturing Vertical Semiconductor Diodes Using An Engineered Substrate

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US Patent:
20200111698, Apr 9, 2020
Filed:
Dec 5, 2019
Appl. No.:
16/704894
Inventors:
- Santa Clara CA, US
Dilip Risbud - San Jose CA, US
Ozgur Aktas - Pleasanton CA, US
Cem Basceri - Los Gatos CA, US
Assignee:
QROMIS, Inc. - Santa Clara CA
International Classification:
H01L 21/683
H01L 21/285
H01L 21/18
H01L 21/762
H01L 29/778
H01L 29/861
H01L 21/02
H01L 21/28
H01L 21/48
H01L 29/10
H01L 29/20
H01L 29/205
H01L 29/417
H01L 29/423
H01L 29/66
C30B 25/18
C30B 29/06
C30B 29/40
H01L 29/872
Abstract:
A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

Electronic Power Devices Integrated With An Engineered Substrate

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US Patent:
20190326148, Oct 24, 2019
Filed:
Jul 1, 2019
Appl. No.:
16/459356
Inventors:
- Santa Clara CA, US
Dilip Risbud - San Jose CA, US
Ozgur Aktas - Pleasanton CA, US
Cem Basceri - Los Gatos CA, US
International Classification:
H01L 21/683
H01L 29/861
C30B 29/06
C30B 25/18
C30B 29/40
H01L 21/28
H01L 29/778
H01L 21/762
H01L 21/48
H01L 29/20
H01L 29/417
H01L 29/423
H01L 29/66
H01L 29/872
H01L 21/02
H01L 29/10
H01L 29/205
H01L 21/285
H01L 21/18
Abstract:
A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.

Systems And Method For Integrated Devices On An Engineered Substrate

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US Patent:
20190172709, Jun 6, 2019
Filed:
Dec 3, 2018
Appl. No.:
16/207793
Inventors:
- Santa Clara CA, US
Dilip Risbud - San Jose CA, US
Ozgur Aktas - Pleasanton CA, US
Cem Basceri - Los Gatos CA, US
Assignee:
QROMIS, Inc. - Santa Clara CA
International Classification:
H01L 21/02
H01L 27/12
H01L 21/84
Abstract:
A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices.

Method And System For Vertical Power Devices

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US Patent:
20180182620, Jun 28, 2018
Filed:
Dec 19, 2017
Appl. No.:
15/847716
Inventors:
- Santa Clara CA, US
Dilip Risbud - San Jose CA, US
Ozgur Aktas - Pleasanton CA, US
Assignee:
QROMIS, Inc. - Santa Clara CA
International Classification:
H01L 21/02
H01L 21/683
H01L 29/66
H01L 21/78
Abstract:
A method of forming a semiconductor device includes providing an engineered substrate. The engineered substrate includes a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer. The method further includes forming a Schottky diode coupled to the engineered substrate. The Schottky diode has a top surface and a bottom surface. the bottom surface is coupled to the substantially single crystalline silicon layer. The method further includes forming a Schottky contact coupled to the top surface of the Schottky diode, forming a metal plating coupled to the Schottky contact, removing the engineered substrate to expose the bottom surface of the Schottky diode, and forming an ohmic contact on the bottom surface of the Schottky diode.

Vertical Semiconductor Diode Manufactured With An Engineered Substrate

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US Patent:
20180061630, Mar 1, 2018
Filed:
Aug 23, 2017
Appl. No.:
15/684753
Inventors:
- Santa Clara CA, US
Dilip Risbud - San Jose CA, US
Ozgur Aktas - Pleasanton CA, US
Cem Basceri - Los Gatos CA, US
Assignee:
Quora Technology, Inc. - Santa Clara CA
International Classification:
H01L 21/02
H01L 29/20
H01L 29/205
H01L 29/872
H01L 29/66
H01L 29/778
C30B 29/06
C30B 29/40
C30B 25/18
Abstract:
A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

Electronic Power Devices Integrated With An Engineered Substrate

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US Patent:
20180061694, Mar 1, 2018
Filed:
Aug 23, 2017
Appl. No.:
15/684724
Inventors:
- Santa Clara CA, US
Dilip Risbud - San Jose CA, US
Ozgur Aktas - Pleasanton CA, US
Cem Basceri - Los Gatos CA, US
Assignee:
Quora Technology, Inc. - Santa Clara CA
International Classification:
H01L 21/683
H01L 21/02
H01L 29/10
H01L 29/417
H01L 29/66
H01L 21/28
H01L 29/20
H01L 29/205
H01L 29/423
H01L 29/778
H01L 29/861
H01L 21/48
Abstract:
A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.

Engineered Substrate Including Light Emitting Diode And Power Circuitry

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US Patent:
20170309676, Oct 26, 2017
Filed:
Apr 19, 2017
Appl. No.:
15/491779
Inventors:
- Santa Clara CA, US
Dilip Risbud - San Jose CA, US
Cem Basceri - Los Gatos CA, US
Assignee:
Quora Technology, Inc. - Santa Clara CA
International Classification:
H01L 27/15
H01L 33/00
H01L 33/00
H01L 33/06
H01L 29/20
H01L 29/778
H01L 33/62
H01L 33/32
Abstract:
A gallium nitride based integrated circuit architecture includes a first electronic device including a first set of III-N epitaxial layers and a second electronic device including a second set of III-N epitaxial layers. The gallium nitride based integrated circuit architecture also includes one or more interconnects between the first electronic device and the second electronic device. The first electronic device and the second electronic device are disposed in a chip scale package.

Aluminum Nitride Based Silicon-On-Insulator Substrate Structure

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US Patent:
20170288055, Oct 5, 2017
Filed:
Mar 28, 2017
Appl. No.:
15/471707
Inventors:
- Santa Clara CA, US
Vladimir Odnoblyudov - Danville CA, US
Dilip Risbud - San Jose CA, US
Cem Basceri - Los Gatos CA, US
Assignee:
Quora Technology, Inc. - Santa Clara CA
International Classification:
H01L 29/78
H01L 29/66
H01L 21/84
H01L 27/12
H01L 29/04
Abstract:
A substrate structure includes a polycrystalline substrate, a plurality of thin film layers disposed on the polycrystalline substrate, a bonding layer coupled to at least a portion of the plurality of thin films, and a single crystal silicon layer joined to the bonding layer.
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Dilip M Risbud from San Jose, CA, age ~65 Get Report