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Denis Tsvetkov Phones & Addresses

  • Durham, NC
  • Raleigh, NC
  • Germantown, MD
  • Morrisville, NC
  • 399 Lochwood Dr, Pittsboro, NC 27312
  • Montgomery Village, MD
  • Lovettsville, VA
  • 11000 Windsor Club Ct APT 30, Raleigh, NC 27617

Resumes

Resumes

Denis Tsvetkov Photo 1

Epi-Sic R And D Engineer

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Location:
Raleigh, NC
Industry:
Semiconductors
Work:
Wolfspeed
Epi-Sic R and D Engineer

National Institute of Standards and Technology Sep 2007 - Jun 2010
Guest Researcher

Cree Sep 2007 - Jun 2010
Sic Epi Process Sustaining Engineer

Kyma Technologies Jun 2003 - Jan 2007
Senior Gan Process Engineer

Tdi 1999 - 2003
Gan Epi-Process Development Engineer
Skills:
Cvd
Characterization
Gan
Thin Films
Nanotechnology
Denis Tsvetkov Photo 2

Denis Tsvetkov

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Publications

Us Patents

Method Of Crystal Growth And Resulted Structures

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US Patent:
6579359, Jun 17, 2003
Filed:
Jun 2, 2000
Appl. No.:
09/585331
Inventors:
Marina Mynbaeva - St. Petersburg, RU
Denis Tsvetkov - Gaithersburg MD
Vladimir Dmitriev - Gaithersburg MD
Alexander Lebedev - St. Petersburg, RU
Nataliya Savkina - St. Petersburg, RU
Alexander Syrkin - Gaithersburg MD
Stephen Saddow - Starkville MI
Karim Mynbaev - St. Petersburg, RU
Assignee:
Technologies and Devices International, Inc. - Gaithersburg MD
International Classification:
C30B 2518
US Classification:
117 94, 117 95, 117107, 117108, 117952
Abstract:
A method is disclosed for fabricating monocrystal material with the bandgap width exceeding 1. 8 eV. The method comprises the steps of processing a monocrystal semiconductor wafer to develop a porous layer through electrolytic treatment of the wafer at direct current under UV-illumination, and epitaxially growing a monocrystal layer on said porous layer. Growth on porous layer produces semiconductor material with reduced stress and better characteristics than with the same material grown on non-porous layers and substrates. Also, semiconductor device structure comprising at least one layer of porous group III material is included.

Method Of Epitaxially Growing Submicron Group Iii Nitride Layers Utilizing Hvpe

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US Patent:
6656272, Dec 2, 2003
Filed:
Mar 28, 2002
Appl. No.:
10/112277
Inventors:
Denis V. Tsvetkov - Gaithersburg MD
Andrey E. Nikolaev - St. Petersburg, RU
Vladimir A. Dmitriev - Gaithersburg MD
Assignee:
Technologies and Devices International, Inc. - Silver Spring MD
International Classification:
C30B 2502
US Classification:
117104
Abstract:
A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i. e. , utilizing the conventional gallium source) and thin layers (i. e. , utilizing the slow growth rate gallium source).

Method Of Epitaxially Growing Device Structures With Submicron Group Iii Nitride Layers Utilizing Hvpe

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US Patent:
6660083, Dec 9, 2003
Filed:
Mar 28, 2002
Appl. No.:
10/113692
Inventors:
Denis V. Tsvetkov - Gaithersburg MD
Andrey E. Nikolaev - St. Petersburg, RU
Vladimir A. Dmitriev - Gaithersburg MD
Assignee:
Technologies and Devices International, Inc. - Silver Spring MD
International Classification:
C30B 2500
US Classification:
117 99, 117 84, 117 88, 117 98, 117107, 117952
Abstract:
A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i. e. , utilizing the conventional gallium source) and thin layers (i. e. , utilizing the slow growth rate gallium source).

Apparatus For Epitaxially Growing Semiconductor Device Structures With Submicron Group Iii Nitride Layer Utilizing Hvpe

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US Patent:
6706119, Mar 16, 2004
Filed:
Mar 28, 2002
Appl. No.:
10/109317
Inventors:
Denis V. Tsvetkov - Gaithersburg MD
Andrey E. Nikolaev - St. Petersburg, RU
Vladimir A. Dmitriev - Gaithersburg MD
Assignee:
Technologies and Devices International, Inc. - Silver Spring MD
International Classification:
C23C 1600
US Classification:
118719, 118726, 118729, 117 91, 117952
Abstract:
A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i. e. , utilizing the conventional gallium source) and thin layers (i. e. , utilizing the slow growth rate gallium source).

Method For Fabricating A P-N Heterojunction Device Utilizing Hvpe Grown Iii-V Compound Layers And Resultant Device

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US Patent:
6890809, May 10, 2005
Filed:
Aug 9, 2002
Appl. No.:
10/217309
Inventors:
Sergey Karpov - St. Petersburg, RU
Alexander Usikov - Silver Spring MD, US
Heikki I. Helava - Piedmont CA, US
Denis Tsvetkov - Gaithersburg MD, US
Vladimir A. Dmitriev - Gaithersburg MD, US
Assignee:
Technologies and Deviles International, Inc. - Silver Spring MD
International Classification:
H01L021/8238
US Classification:
438200, 438201, 438604, 257 12, 257 13, 257 14, 257 15, 257 16, 257 17, 257 22
Abstract:
A method for fabricating a p-n heterojunction device is provided, the device being preferably comprised of an n-type GaN layer co-doped with silicon and zinc and a p-type AlGaN layer. The device may also include a p-type GaN capping layer. The device can be grown on any of a variety of different base substrates, the base substrate comprised of either a single substrate or a single substrate and an intermediary layer. The device can be grown directly onto the surface of the substrate without the inclusion of a low temperature buffer layer.

Manufacturing Methods For Semiconductor Devices With Multiple Iii-V Material Layers

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US Patent:
6955719, Oct 18, 2005
Filed:
Jul 18, 2003
Appl. No.:
10/623375
Inventors:
Vladimir A. Dmitriev - Gaithersburg MD, US
Denis V. Tsvetkov - Gaithersburg MD, US
Aleksei Pechnikov - North Potomac MD, US
Yuri V. Melnik - Rockville MD, US
Aleksandr Usikov - Silver Spring MD, US
Oleg Kovalenkov - Gaithersburg MD, US
Assignee:
Technologies and Devices, Inc. - Silver Springs MD
International Classification:
C30B025/00
US Classification:
117 91, 117 84, 117 88, 117 89, 117 99, 117 98, 117107, 117952
Abstract:
A method for fabricating semiconductor devices with thin (e. g. , submicron) and/or thick (e. g. , between 1 micron and 100 microns thick) Group III nitride layers during a single epitaxial run is provided, the layers exhibiting sharp layer-to-layer interfaces. According to one aspect, an HVPE reactor is provided that includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor is provided that includes at least one growth zone as well as a growth interruption zone. According to another aspect, an HVPE reactor is provided that includes extended growth sources such as slow growth rate gallium source with a reduced gallium surface area. According to another aspect, an HVPE reactor is provided that includes multiple sources of the same material, for example Mg, which can be used sequentially to prolong a growth cycle.

Apparatus For Epitaxially Growing Semiconductor Device Structures With Sharp Layer Interfaces Utilizing Hvpe

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US Patent:
7670435, Mar 2, 2010
Filed:
Mar 28, 2002
Appl. No.:
10/113222
Inventors:
Denis V. Tsvetkov - Gaithersburg MD, US
Andrey E. Nikolaev - St. Petersburg, RU
Vladimir A. Dmitriev - Gaithersburg MD, US
Assignee:
Technologies and Devices International, Inc. - Silver Spring MD
International Classification:
C23C 16/00
US Classification:
118726, 118719, 118724, 118725, 118729
Abstract:
A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i. e. , utilizing the conventional gallium source) and thin layers (i. e. , utilizing the slow growth rate gallium source).

Inclusion-Free Uniform Semi-Insulating Group Iii Nitride Substrate And Methods For Making Same

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US Patent:
7777217, Aug 17, 2010
Filed:
Nov 30, 2006
Appl. No.:
11/606633
Inventors:
Edward A. Preble - Raleigh NC, US
Denis Tsvetkov - Morrisville NC, US
Andrew D. Hanser - Raleigh NC, US
N. Mark Williams - Raleigh NC, US
Xueping Xu - Stamford CT, US
Assignee:
Kyma Technologies, Inc. - Raleigh NC
International Classification:
H01L 31/00
US Classification:
257 21, 257 79, 257189, 257646, 257E33025
Abstract:
In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.
Denis V Tsvetkov from Durham, NC, age ~55 Get Report