David L Questad

6348738, Feb 19, 2002

Aug 11, 1999

09/371975

Jean Dery - Granby, CA
Frank D. Egitto - Binghamton NY
Luis J. Matienzo - Endicott NY
Charles Ouellet - Missisquoi, CA
Luc Ouellet - Bromont, CA
David L. Questad - Vestal NY
William J. Rudik - Vestal NY
Son K. Tran - Endwell NY

International Business Machines Corporation - Armonk NY

H01L 2348

257778, 257737, 257738, 257734, 257784, 257786, 257787, 257777

A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O plasma or a microwave-generated Ar and N O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously.

6607613, Aug 19, 2003

Feb 1, 2001

09/775747

Frank D. Egitto - Binghampton NY
Edmond O. Fey - Vestal NY
Luis J. Matienzo - Endicott NY
David L. Questad - Vestal NY
Rajinder S. Rai - Johnson City NY
Daniel C. Van Hart - Conklin NY

International Business Machines Corporation - Armonk NY

C22C 1106

148400, 148241, 148280, 228 42, 228205, 228217, 428547, 428610, 20419217, 20419235

A metal alloy solder ball comprising a first metal and a second metal, the first metal having a sputtering yield greater than the second metal. The solder ball comprises a bulk portion having a bulk ratio of the first metal to the second metal, an outer surface, and a surface gradient having a depth and a gradient ratio of the first metal to the second metal that is less than the bulk ratio. The gradient ratio increases along the surface gradient depth from a minimum at the outer surface. The solder ball may be formed by the process of exposing the ball to energized ions of a sputtering gas for an effective amount of time to form the surface gradient.

6650010, Nov 18, 2003

Feb 15, 2002

10/078174

Charles R. Davis - Fishkill NY
David L. Hawken - Vestal NY
Dae Young Jung - LaGrangeville NY
William F. Landers - Wappingers Falls NY
David L. Questad - Vestal NY

International Business Machines Corporation - Armonk NY

H01L 2312

257700, 257701, 257774, 257758, 257759

A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

6815346, Nov 9, 2004

May 13, 2003

10/437208

Charles R. Davis - Fishkill NY
David L. Hawken - Vestal NY
Dae Young Jung - LaGrangeville NY
William F. Landers - Wappingers Falls NY
David L. Questad - Vestal NY

International Business Machines Corporation - Armonk NY

H01L 2144

438666, 438622, 438623, 438637

A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

6979782, Dec 27, 2005

May 9, 2005

10/908353

William L. Brodsky - Binghamton NY, US
David L. Questad - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H01L023/02

174 524, 257704

A land grid array (LGA) assembly includes a chip carrier substrate having at least one chip attached thereto, and a stiffener member attached to the chip carrier substrate, the stiffener member further including a honeycomb material. A cap is attached to the chip and stiffener member.

7059049, Jun 13, 2006

Sep 24, 2002

10/253725

Donald S. Farquhar - Endicott NY, US
James D. Herard - Vestal NY, US
Michael J. Klodowski - Endicott NY, US
David Questad - Vestal NY, US

International Business Machines Corporation - Armonk NY

H01K 3/10

29852, 29846, 29830, 29831, 29832, 361795, 361792, 361793, 361794, 361748, 174255, 174266, 174262, 257700, 257698, 438125

An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature Tand a maximum temperature T. Tconstrains the ductility of the first dielectric layer to be at least Dfollowing the laminating. Tdepends on Dand on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature Tand a maximum temperature T. Tconstrains the ductility of the second dielectric layer to be at least Dfollowing the laminating. Tdepends on Dand on a second dielectric material comprised by the second dielectric layer.

7312523, Dec 25, 2007

Jul 28, 2005

11/161285

Jean J. Audet - Quebec, CA
Jon A. Casey - Poughkeepsie NY, US
Luc Guerin - Quebec, CA
David L. Questad - Hopewell Junction NY, US
David J. Russell - Owego NY, US

International Business Machines Corporation - Armonk NY

H01L 23/053
H01L 23/12
H01L 23/48

257700, 257701, 257774, 257E23011

A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer; and a plurality of via lands extending radially outward from the via stack, wherein each of the plurality of via lands is diametrically larger than the RFP cap. Preferably, the RFP cap comprises a diameter of at least 300 μm. Preferably, each of the via lands comprises a substantially circular shape having a diameter of at least 400 μm. Moreover, the circuit board further comprises a ball grid array pad connected to the via stack; and input/output ball grid array pads connected to the ball grid array pad. Additionally, the circuit board further comprises metal planes in the dielectric layer.

7319591, Jan 15, 2008

May 26, 2005

10/908796

Jeffrey T. Coffin - Pleasant Valley NY, US
Michael A. Gaynes - Vestal NY, US
David L. Questad - Hopewell Junction NY, US
Kamal K. Sikka - Poughkeepsie NY, US
Hilton T. Toy - Hopewell Junction NY, US
Jamil A. Wakil - Wappingers Falls NY, US

International Business Machines Corporation - Armonk NY

H05K 7/20

361705

Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.