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David L Kencke

from Beaverton, OR
Age ~56
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Also known as:
David Leighton Kencke, David W Kencke, Dave Kencke
Phone and address:
3839 163Rd Ave, Beaverton, OR 97006
(503) 466-0199
Related to:
James H Spurlock, 55Marianne E Chernesky, 47Peter R Conrad, 51Joshua J Chernesky, 48Ruth KenckeErica H Kencke, 64E Kencke, 64Edna R KenckeJudith January Kencke, 81
Connected to:
Victoria R Kenda, 35Deana A Kendadi, 53Solomon K Kendagor, 73Balakumar K Kendai, 45Curtis K Kendal, 47Natasha Kendal, 51Philip J Kendal, 91Scott Kendal, 81Tom Kendal, 43Adam D Kendall, 46

David Kencke Phones & Addresses

  • 3839 163Rd Ave, Beaverton, OR 97006 (503) 466-0199 (503) 617-7354
  • 3839 163Rd Ter, Beaverton, OR 97006 (503) 617-7354 (503) 548-7456
  • 5465 Innisbrook Pl, Portland, OR 97229
  • Austin, TX
  • 6914 Flintcove Dr, Dallas, TX 75248 (972) 661-9430
  • 3839 NW 163Rd Ter, Beaverton, OR 97006 (503) 617-7354

Work

Company: Intel corporation Jul 1, 2015 Position: Co-manager, device and process applications, tcad

Education

Degree: Doctorates, Doctor of Philosophy School / High School: The University of Texas at Austin 1995 to 2000 Specialities: Computer Engineering, Philosophy

Skills

Simulations • Semiconductors • C • Physics • Thin Films • Materials Science • Nanotechnology • Debugging • Design of Experiments • Ic • Integrated Circuits • Characterization

Industries

Semiconductors

Resumes

Resumes

David Kencke Photo 1

Co-Manager, Device And Process Applications, Tcad

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corporation
Co-Manager, Device and Process Applications, Tcad

Co-Manager, Device and Process Applications, Tcad
Intel Corporation
Software Engineer
Education:
The University of Texas at Austin 1995 - 2000
Doctorates, Doctor of Philosophy, Computer Engineering, Philosophy The University of Texas at Austin 1993 - 1995
Master of Science, Masters, Computer Engineering, Engineering Wheaton College 1985 - 1990
Bachelors, Bachelor of Science, Physics, Philosophy
Skills:
Simulations
Semiconductors
C
Physics
Thin Films
Materials Science
Nanotechnology
Debugging
Design of Experiments
Ic
Integrated Circuits
Characterization

Publications

Us Patents

Biasing Scheme Of Floating Unselected Wordlines And Bitlines Of A Diode-Based Memory Array

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US Patent:
6462984, Oct 8, 2002
Filed:
Jun 29, 2001
Appl. No.:
09/895599
Inventors:
Daniel Xu - Mountain View CA
Tyler A. Lowrey - San Jose CA
David L. Kencke - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1136
US Classification:
365175, 365174, 365163, 365148, 365203, 3652257, 365 51
Abstract:
An integrated circuit (IC) has a number of memory cells, each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell. A target memory cell of the IC is programmed while simultaneously floating a number of unselected bitlines and wordlines in the IC.

Hetero-Bimos Injection Process For Non-Volatile Flash Memory

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US Patent:
7598560, Oct 6, 2009
Filed:
Mar 30, 2007
Appl. No.:
11/731162
Inventors:
Jack T. Kavalieros - Portland OR, US
Suman Datta - Beaverton OR, US
Robert S. Chau - Beaverton OR, US
David L. Kencke - Beaverton OR, US
International Classification:
H01L 29/76
H01L 29/788
US Classification:
257314, 257326, 257E29129
Abstract:
A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor.

Asymmetric Channel Doping For Improved Memory Operation For Floating Body Cell (Fbc) Memory

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US Patent:
7646071, Jan 12, 2010
Filed:
May 31, 2006
Appl. No.:
11/444941
Inventors:
Ibrahim Ban - Beaverton OR, US
Avci E. Uygar - Beaverton OR, US
David L. Kencke - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/76
US Classification:
257404, 257345, 257347, 257341, 257335, 257E29053
Abstract:
An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage.

Multiple Oxide Thickness For A Semiconductor Device

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US Patent:
7719057, May 18, 2010
Filed:
Jul 30, 2007
Appl. No.:
11/830182
Inventors:
Martin D Giles - Portland OR, US
David L Kencke - Beaverton OR, US
Stephen M Cea - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 27/01
H01L 27/12
H01L 31/0392
US Classification:
257347, 257157, 257E21415
Abstract:
Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of the fin, and a second oxide having a second thickness coupled with a second side of the fin, the second thickness being different from the first thickness as a result of the impurity introduced to the first side of the fin.

Asymmetric Channel Doping For Improved Memory Operation For Floating Body Cell (Fbc) Memory

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US Patent:
7944003, May 17, 2011
Filed:
Nov 30, 2009
Appl. No.:
12/627855
Inventors:
Ibrahim Ban - Beaverton OR, US
Avci E. Uygar - Beaverton OR, US
David L. Kencke - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/76
US Classification:
257404, 257345, 257347, 257341, 257335, 257E2953
Abstract:
An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage.

Phase Change Memory With Layered Insulator

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US Patent:
8076664, Dec 13, 2011
Filed:
Dec 20, 2007
Appl. No.:
12/004257
Inventors:
Semyon D. Savransky - Newark CA, US
David L. Kencke - Beaverton OR, US
Ilya V. Karpov - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/04
H01L 47/00
H01L 29/00
H01L 29/02
H01L 29/06
G11C 11/00
US Classification:
257 3, 257 1, 257 2, 257 4, 257 5, 365148
Abstract:
A phase change memory may be formed with an insulator made up of two different layers having significantly different thermal conductivities. Pores may be formed within the stack of insulating layers and the pores may be filled with heaters, chalcogenide layers, and electrodes in some embodiments. The use of the two different insulator layers enables embodiments where thermal losses may be reduced and an amorphous region may be maintained along the entire length of the phase change material layer.

Floating Body Memory Cell Having Gates Favoring Different Conductivity Type Regions

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US Patent:
8217435, Jul 10, 2012
Filed:
Dec 22, 2006
Appl. No.:
11/644715
Inventors:
Peter L. D. Chang - Portland OR, US
Uygar E. Avci - Beaverton OR, US
David L. Kencke - Beaverton OR, US
Ibrahim Ban - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/76
H01L 29/66
H01L 27/088
H01L 21/00
H01L 21/84
H01L 21/336
H01L 21/8234
H01L 21/8238
US Classification:
257288, 257331, 257401, 257903, 257E21625, 257E21639, 257E2706, 438157, 438197
Abstract:
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Floating Body Memory Cell Having Gates Favoring Different Conductivity Type Regions

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US Patent:
8569812, Oct 29, 2013
Filed:
Jun 27, 2012
Appl. No.:
13/534985
Inventors:
Peter L. D. Chang - Portland OR, US
Uygar E. Avci - Beaverton OR, US
David L. Kencke - Beaverton OR, US
Ibrahim Ban - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/76
H01L 29/66
H01L 27/088
H01L 21/00
H01L 21/84
H01L 21/336
H01L 21/8234
H01L 21/8238
US Classification:
257288, 257331, 257401, 257903, 257E21625, 257E21639, 257E2706, 438157, 438197
Abstract:
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
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David L Kencke from Beaverton, OR, age ~56 Get Report