David Ford

58188908, Oct 6, 1998

Sep 24, 1996

8/719423

David K. Ford - Gilbert AZ
Philip A. Jeffery - Tempe AZ
Phuc C. Pham - Chandler AZ

Motorola, Inc. - Schaumburg IL

H03D 324

375371

A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal using serially connected delay elements (21-27). The delayed versions of the serial data signal are sampled using a set of flip-flops (11-18). The sampled delayed data signals appearing at the outputs of each flip-flop of the set of flip-flops (11-18) are used to determine which delayed data signal is most closely aligned to the clock signal. The output of the multiplexer (40) is an aligned serial data signal. In addition, a drift correction circuit (50) continuously monitors and corrects the alignment between the clock signal and the aligned serial data signal.

54184967, May 23, 1995

Feb 7, 1994

8/192521

David Ford - Gilbert AZ
Emil N. Hahn - Gilbert AZ
Michael D. Reed - Mesa AZ
Nandini Srinivasan - Chandler AZ
Philip A. Jeffrey - Tempe AZ

Motorola, Inc. - Schaumburg IL

H03L 7099
H04L 708

331 2

A serial data clock receiver circuit (11) is provided that synchronizes a clock signal to data. The serial data clock receiver circuit (11) comprises a control circuit (21), a dual oscillator circuit (19), and a phase locked loop circuit (22). The control circuit (21) arms the dual oscillator circuit (19) for being enabled during an idle period. The phase locked loop circuit (22) provides a reference voltage for the dual oscillator circuit (19). The dual oscillator circuit (19) is responsive to both the data and control circuit (19) for providing a clock signal.

61817570, Jan 30, 2001

Apr 27, 1998

9/067757

Roland Neumann - Holzkirchen, DE
Phil Jeffery - Tempe AZ
David Ford - Gilbert AZ

Motorola Inc. - Schaumburg IL

H03D 324

375375

Retiming means for retiming an incoming data stream 2 comprising clock generation means 22 for producing a plurality of clock signals 23 having the same frequency but differing phase, and signal processing means 24 for receiving both the plurality of clock signals 23 and the incoming data stream 2 and outputting a selected one of the clock signals 23 and a retimed data stream retimed in accordance with the selected clock signal. The signal processing means 24 includes comparison means for comparing the phase of the incoming data stream with the phase of the plurality of clock signals and selecting which clock signal to use on the basis of this comparison.

55635946, Oct 8, 1996

Aug 31, 1994

8/298715

David K. Ford - Gilbert AZ
Bernard E. Weir - Chandler AZ

Motorola - Schaumburg IL

H03M 900

341100

A data conversion circuit receives input data from external sourcing logic and performs a parallel-serial conversion. Likewise, a data conversion circuit performs a serial-parallel conversion and presents output data to external sinking logic. In the parallel-serial conversion (10), the input data is translated (12) and stored in a register (14). A multiplexer (16) rotates through the data to provide the serial output. In the serial-parallel conversion (70), the input data is sequenced into a multiplexer (74) to achieve the parallel data word. The parallel data word is stored in a register (76) before presenting it to external logic. Phase delay logic (22) sets the delay of a transfer data control signal that requests data be read or written. Once the proper delay is determined by experimentation, the phase delay logic controls the phase of the transfer data control signal to request more data at the correct time, or present more data at the correct time, to allow maximum operating speed for the data converter.

55482856, Aug 20, 1996

Jul 18, 1994

8/276373

David K. Ford - Gilbert AZ
Bernard E. Weir - Chandler AZ

Motorola, Inc. - Schaumburg IL

H03M 900

341100

A parallel to serial converter (10) uses a data hold-time indicator (22) to indirectly observe the timing relationship of the data and clock applied to a data register (14) embedded within an integrated circuit. The incoming data word is converted from CMOS to ECL logic levels (12) and applied to the data register. The register holds data for a multiplexer (16) that rotates through the output data from the register for providing a serial data output signal. A flipflop circuit (18) clocks the serial data output signal. The data hold-time indicator circuit monitors one register input and generates a recurring pulse having a width that reflects the data hold-time at the embedded register. By indirectly observing the timing relationship, the externally sourced data timing can be calibrated to meet the setup and hold-time requirements of the data register.