Resumes
Resumes
Daniel Prager Phones & Addresses
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Saratoga Springs, NY
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Ballston Spa, NY
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Wilton, NY
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89 Shagbark Ln, Hopewell Junction, NY 12533 (845) 227-5711 (845) 227-5712
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East Fishkill, NY
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Hyde Park, NY
Publications
Us Patents
Iso/Nested Cascading Trim Control With Model Feedback Updates
View pageUS Patent:
7209798, Apr 24, 2007
Filed:
Sep 20, 2004
Appl. No.:
10/944463
Inventors:
Asao Yamashita - Wappingers Falls NY, US
Merritt Lane Funk - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Merritt Lane Funk - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
G06F 19/00
US Classification:
700121, 738714
Abstract:
This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.
Feature Dimension Deviation Correction System, Method And Program Product
View pageUS Patent:
7289864, Oct 30, 2007
Filed:
Jul 12, 2004
Appl. No.:
10/710447
Inventors:
David V. Horak - Essex Junction VT, US
Wesley C. Natzle - New Paltz NY, US
Merritt L. Funk - Austin TX, US
Kevin J. Lally - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Wesley C. Natzle - New Paltz NY, US
Merritt L. Funk - Austin TX, US
Kevin J. Lally - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
Tokyo Electron Limited - Tokyo
Tokyo Electron Limited - Tokyo
International Classification:
G06F 19/00
US Classification:
700121, 356625, 438 14, 700110
Abstract:
A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.
Using A Virtual Profile Library
View pageUS Patent:
7305322, Dec 4, 2007
Filed:
Mar 31, 2006
Appl. No.:
11/396112
Inventors:
Merritt Funk - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Daniel Prager - Hopewell Junction NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
G01B 7/00
G01B 11/02
G01B 11/02
US Classification:
702155, 356511
Abstract:
To determine the profile of an integrated circuit structure, a signal is measured off the structure with a metrology device. The measured signal is compared to signals in a virtual profile library. The comparison is stopped if matching criteria are met. A subset of a virtual profile data space is determined when the matching criteria are not met. The subset is determined using profile data space associated with the library. A virtual profile signal of the subset is selected. Virtual profile shape/parameters are determined based on the virtual profile signal. A difference is calculated between the measured and virtual profile signals. The difference is compared to virtual profile library creation criteria. If the criteria are met, then the structure is identified using virtual profile data, which includes the virtual profile shape/parameters, associated with the virtual profile signal. Or, if the criteria are not met, then a corrective action is applied.
Iso/Nested Control For Soft Mask Processing
View pageUS Patent:
7328418, Feb 5, 2008
Filed:
Feb 1, 2005
Appl. No.:
11/046903
Inventors:
Asao Yamashita - Wappingers Falls NY, US
Merritt Funk - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Merritt Funk - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
G06F 17/50
G06F 9/45
G06F 9/45
US Classification:
716 10, 716 1, 716 19
Abstract:
This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.
Optical Metrology Model Optimization For Process Control
View pageUS Patent:
7395132, Jul 1, 2008
Filed:
May 21, 2007
Appl. No.:
11/804998
Inventors:
Daniel Prager - Hopewell Junction NY, US
Jason Ferns - Sunnyvale CA, US
Lawrence Lane - San Jose CA, US
Dan Engelhard - Mountain View CA, US
Jason Ferns - Sunnyvale CA, US
Lawrence Lane - San Jose CA, US
Dan Engelhard - Mountain View CA, US
Assignee:
Timbre Technologies, Inc. - Santa Clara CA
International Classification:
G06F 19/00
US Classification:
700108
Abstract:
To evaluate the adequacy of a profile model, an initial profile model is selected. The profile model includes profile model parameters to be measured in implementing types of process control to be used in controlling a fabrication process. A measurement of profile model parameters is obtained using a first metrology tool and the profile model. A measurement of the profile model parameters is obtained using a second metrology tool and the profile model. Statistical metric criteria are calculated based on the measurements of the profile model parameters obtained using the first and second metrology tools. When the calculated statistical metric criteria are not within matching requirements, the profile model is revised. When the calculated statistical metric criteria are within matching requirements, the profile model or the revised profile model is stored.
Refining A Virtual Profile Library
View pageUS Patent:
7487053, Feb 3, 2009
Filed:
Mar 31, 2006
Appl. No.:
11/394860
Inventors:
Merritt Funk - Austin TX, US
Daniel J. Prager - Hopewell Junction NY, US
Daniel J. Prager - Hopewell Junction NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
G01F 19/00
US Classification:
702 66
Abstract:
A method of refining a virtual profile library includes obtaining a reference signal measured off a reference structure on a semiconductor wafer with a metrology device. A best match is selected of the reference signal in a virtual profile data space. The virtual profile data space has data points with specified accuracy values. The data points represent virtual profile parameters and associated virtual profile signals. The virtual profile parameters characterize the profile of an integrated circuit structure. The best match being a data point of the profile data space with a signal closest to the reference signal. Refined virtual profile parameters are determined corresponding to the reference signal based on the virtual profile parameters of the selected virtual profile signal using a refinement procedure.
Feature Dimension Deviation Correction System, Method And Program Product
View pageUS Patent:
7502660, Mar 10, 2009
Filed:
Oct 2, 2007
Appl. No.:
11/865739
Inventors:
David V. Horak - Essex Junction VT, US
Wesley C. Natzle - New Paltz NY, US
Merritt L. Funk - Austin TX, US
Kevin J. Lally - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Wesley C. Natzle - New Paltz NY, US
Merritt L. Funk - Austin TX, US
Kevin J. Lally - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
Tokyo Electron Limited - Tokyo
Tokyo Electron Limited - Tokyo
International Classification:
G06F 19/00
US Classification:
700121, 356625, 438 14, 700110
Abstract:
A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.
Dynamic Metrology Sampling For A Dual Damascene Process
View pageUS Patent:
7502709, Mar 10, 2009
Filed:
Mar 28, 2006
Appl. No.:
11/390412
Inventors:
Merritt Funk - Austin TX, US
Radha Sundararajan - Dripping Springs TX, US
Daniel Joseph Prager - Hopewell Junction NY, US
Wesley Natzle - New Paltz NY, US
Radha Sundararajan - Dripping Springs TX, US
Daniel Joseph Prager - Hopewell Junction NY, US
Wesley Natzle - New Paltz NY, US
Assignee:
Tokyo Electron, Ltd. - Tokyo
International Business Machines Corporation - Armonk NY
International Business Machines Corporation - Armonk NY
International Classification:
G06F 3/00
US Classification:
702127, 702128, 702183
Abstract:
A method of monitoring a dual damascene procedure that includes calculating a pre-processing confidence map for a damascene process, the pre-processing confidence map including confidence data for a first set of dies on the wafer. An expanded pre-processing measurement recipe is established for the damascene process when one or more values in the pre-processing confidence map are not within confidence limits established for the damascene process. A reduced pre-processing measurement recipe for the first damascene process is established when one or more values in the pre-processing confidence map are within confidence limits established for the damascene process.