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Damon Koehler Phones & Addresses

  • 88 Sunnyside Dr, San Leandro, CA 94577 (510) 878-7730
  • Kailua Kona, HI
  • 39601 Fremont Blvd, Fremont, CA 94538
  • Milpitas, CA
  • San Jose, CA
  • Ayr, NE
  • Grandview, MO
  • Hastings, NE
  • Kansas City, MO
  • Alameda, CA

Work

Company: Ultra clean technology Feb 2007 Position: Npi program manager

Education

Specialities: Electrical Engineering

Skills

Manufacturing • Semiconductors • Electronics • Cross Functional Team Leadership • Troubleshooting • Engineering • Continuous Improvement • Testing • Engineering Management • Product Development • Manufacturing Engineering • Systems Engineering • Program Management • Process Improvement • Process Engineering • Product Management • Design For Manufacturing

Languages

English

Industries

Semiconductors

Resumes

Resumes

Damon Koehler Photo 1

Senior Npi Program Manager

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Location:
88 Sunnyside Dr, San Leandro, CA 94577
Industry:
Semiconductors
Work:
Ultra Clean Technology since Feb 2007
NPI Program Manager

Metara, Inc. Jul 2005 - Feb 2007
Manufacturing Test Engineer

ACM Research, Inc. May 2001 - Jul 2005
Sr. Systems Engineer

Quester Technology 1994 - 2001
Software Quality Engineer

Dwyer Instruments Nov 1991 - Nov 1994
Assembler
Education:
Hartington Public H.s
Skills:
Manufacturing
Semiconductors
Electronics
Cross Functional Team Leadership
Troubleshooting
Engineering
Continuous Improvement
Testing
Engineering Management
Product Development
Manufacturing Engineering
Systems Engineering
Program Management
Process Improvement
Process Engineering
Product Management
Design For Manufacturing
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Damon Koehler
Npi Project Manager
ULTRA CLEAN HOLDINGS INC
Manufactures Semiconductors & Related Devices · Mfg Semiconductors & Related Devices
26462 Corporate Ave, Hayward, CA 94545
2642 Corporate Ave, Hayward, CA 94545
(510) 576-4400, (510) 576-4401

Publications

Us Patents

Adaptive Electropolishing Using Thickness Measurement And Removal Of Barrier And Sacrificial Layers

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US Patent:
20050245086, Nov 3, 2005
Filed:
Jul 22, 2003
Appl. No.:
10/520493
Inventors:
Hui Wang - Fremont CA, US
Muhammed Afnan - Fremont CA, US
Peihaur Yih - Boonton NJ, US
Damon Koehler - Fremont CA, US
Chaw-Chi Yu - Saratoga CA, US
Assignee:
ACM Research, Inc. - Fremont CA
International Classification:
H01L021/302
H01L021/461
US Classification:
438690000
Abstract:
A metal layer formed on a semiconductor wafer is adaptively electropolished. A portion of the metal layer is electropolished, where portions of the metal layer are electropolished separately. Before electropolishing the portion, a thickness measurement of the portion of the metal layer to be electropolished is determined. The amount that the portion is to be electropolished is adjusted based on the thickness measurement. A metal layer formed on a semiconductor wafer is polished, where the metal layer is formed on a barrier layer, which is formed on a dielectric layer having a recessed area and a non-recessed area, and where the metal layer covers the recessed area and the non-recessed areas of the dielectric layer. The metal layer is polished to remove, the metal layer covering the non-recessed area. The metal layer in the recessed area is polished to a height below the non-recessed area, where the height is equal to or greater than a thickness of the barrier layer.
Damon Lane Koehler from San Leandro, CA, age ~51 Get Report