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Curtis L Cornils

from Chandler, AZ
Age ~70
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Also known as:
Curtis Lee Cornils, Curtis C Cornils, Curtis J Cornils, Curtis L Cornill, Curt Cornils, Jerri Cornils, Jerri Curtis, Curtis S, Cornils Connor
Related to:
Jerri L Cornils, 66Jody A Miller, 68Connor J Cornils, 33
Connected to:
Britta Cornils, 54Jay A Cornils, 74Jessie L Cornils, 38Alice E Corning, 72Alison Corning, 53Anita J Corning, 66Candida M Corning, 47Cathy A Corning, 65Cecil C Corning, 66

Curtis Cornils Phones & Addresses

  • Chandler, AZ
  • Phoenix, AZ
  • Pinetop, AZ
  • 1345 Hopi Ave, Mesa, AZ 85204
  • Scottsdale, AZ
  • Tempe, AZ
  • 1754 W San Tan St, Chandler, AZ 85224

Interests

career opportunities, consulting offers,...

Industries

Defense & Space

Resumes

Resumes

Curtis Cornils Photo 1

Member Technical Staff At General Dynamics

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Location:
Phoenix, Arizona Area
Industry:
Defense & Space
Experience:
General Dynamics (Public Company; 10,001+ employees; GD; Defense & Space industry): Member Technical Staff,  (-) 

Publications

Us Patents

Method And Apparatus For A Mapping Receiver

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US Patent:
6400927, Jun 4, 2002
Filed:
Aug 30, 1999
Appl. No.:
09/385555
Inventors:
Brian M. Daniel - Phoenix AZ
Curtis L. Cornils - Chandler AZ
Keith A. Olds - Mesa AZ
Ray O. Waddoups - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04B 7185
US Classification:
455 131, 455 63, 455428, 455430, 370316
Abstract:
A satellite ground station ( ) mitigates potential interference from a fixed service installation ( ) by scanning a field of view and logging potentially interfering transmitters in a data structure ( ). The data structure includes fields for azimuth, elevation, and frequency channel, and when complete, forms a map of potentially interfering transmitters within the field of view of the ground station. When a satellite traverses the field of view such that the ground station may interfere with, or be interfered with by, a known potentially interfering transmitter as identified in the map, the ground station takes mitigation measures such as changing frequency channels or handing-off to a different satellite.

Array Of Processors Architecture For A Space-Based Network Router

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US Patent:
6711407, Mar 23, 2004
Filed:
Jul 13, 2000
Appl. No.:
09/615307
Inventors:
Curtis Lee Cornils - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04Q 720
US Classification:
455428, 455427, 455112, 370315, 370316, 370325, 370323, 370319, 370401, 370285, 370258
Abstract:
A space-based network router architecture ( ) is disclosed. The router includes an array-of-processors architecture ( ) for routing uplink and downlink traffic of a communications system ( ). The architecture comprises multiple node interface chips ( ) linked to one another via horizontal and vertical rings ( ), thus forming a mesh ( ). Associated with each node interface chip ( ) is a processor ( ) and either a demodulator ( ) or modulator ( ). Each node interface chip ( ) selectively transfers a signal depending upon the particular signals destination and processing requirements. The router architecture ( ) provides scalabitly, fault-tolerance and flexibility, as well as structural advantages over present router systems.

Network Compromise Recovery Methods And Apparatus

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US Patent:
7065643, Jun 20, 2006
Filed:
Mar 28, 2000
Appl. No.:
09/536577
Inventors:
Curtis Lee Cornils - Chandler AZ, US
Erwin Perry Comer - Queen Creek AZ, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04K 1/00
H04L 9/12
H04L 9/00
US Classification:
713163, 380273, 380279, 380284
Abstract:
A secure communications system (, FIG. ) with a compromised communications node can quickly recover from the compromised condition by sending re-keying messages using a key encryption key hierarchy (, FIG. ). Each communications node (, FIG. ) includes a memory (, FIG. ) with a list of tier-group specific key encryption keys, and whenever a message arrives that is encrypted with a key encryption key in the list, the communications node decrypts the message. When the message includes a new traffic encryption key, the communications node has been re-keyed. Key encryption keys are managed hierarchically such that many communications nodes can be re-keyed with very few broadcast messages, thereby saving communications resources.

Methods And Apparatus For Supporting A Half-Duplex Mode Of Operation For User Equipment Communications In A Radio Communication System

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US Patent:
8036137, Oct 11, 2011
Filed:
Nov 25, 2008
Appl. No.:
12/323182
Inventors:
Daniel Bruce Bossler - Chandler AZ, US
Scott Dave Blanchard - Mesa AZ, US
Curtis Lee Cornils - Chandler AZ, US
Assignee:
General Dynamics C4 Systems, Inc. - Scottsdale AZ
International Classification:
H04L 12/26
US Classification:
370252, 370316, 370350
Abstract:
Embodiments include methods performed in time division duplex (TDD) radio communication systems in which information is communicated between a first node (e. g. , a base) and a second node (e. g. , user equipment) in a context of a data frame that includes a plurality of slots. The second node applies an adjustment to an alignment between a second node transmit clock and a second node receive clock based on a propagation delay between the first node and the second node. The adjusted alignment ensures that second node receive slots and second node transmit slots are non-overlapping with each other in time, and that the second node will operate in a half-duplex mode of operation. The second node transmits a transmit burst during the second node transmit slots, and receives a first node transmit burst from the first node during the second node receive slots.

Isolated Multiprocessing System Having Tracking Circuit For Verifyng Only That The Processor Is Executing Set Of Entry Instructions Upon Initiation Of The System Controller Program

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US Patent:
55510515, Aug 27, 1996
Filed:
Sep 20, 1994
Appl. No.:
8/309379
Inventors:
Lee Silverthorn - Paradise Valley AZ
Curtis Cornils - Phoenix AZ
Mark L. Kirchner - Phoenix AZ
Susan D. Stephens - Chandler AZ
Parker E. Crouse - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1500
G06F 1200
G06F 1312
US Classification:
395800
Abstract:
A computer (20) includes a hardware memory access enforcer (50) to insure that various independent programs (52, 54) operating on the computer (20) follow isolated processing rules. Each program has its own memory domain (56), which may extend across instruction, data, and I/O memory spaces (40, 42, 44). A system controller program (52) is a trusted process. The system controller (52) may access memory in the domain (56) of any application (54), and program flow may exit system controller (52) to any application (54). However, applications (54) cannot access memory outside of their own domains (56), and program flow may not exit applications (54) to enter other applications (54). Program flow may exit applications (54) to system controller (52) only if directed to an entry address (60). A tracking circuit (74) verifies that a microprocessor (22) actually executes entry instructions (94) located at the entry address (60).

Secure Bus Arbiter Interconnect Arrangement

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US Patent:
60981334, Aug 1, 2000
Filed:
Nov 28, 1997
Appl. No.:
8/980296
Inventors:
Mark David Summers - Phoenix AZ
Donald Charles Cohlman - Chandler AZ
John Paul Sharrit - Fountain Hills AZ
Curtis Lee Cornils - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1300
US Classification:
710107
Abstract:
An apparatus is provided to handle classes of data in computer systems that must not be permitted to intermingle due to their security classifications or criticality of their data content, as in banking or safety applications. An isolated path is established for transmitting a given class of data between elements of the computer system with assurance that the data has been transmitted from the proper source, has been received by an authorized recipient and that unauthorized elements of the system have not intercepted or altered the data. Plug in type secure bus arbiter (SBA) module or bus arbiter interconnect module (10) with a controller (11) provide a way to isolate data without modification of the computer back plane or motherboard in a computer chassis (12). Modules can be used with commercial off the shelf (COTS) and non-development item (NDI) cards for a wide variety of standard computer printed circuit boards.

Channel Isolation Arrangement And Method For Dissociated Data

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US Patent:
59448229, Aug 31, 1999
Filed:
Aug 18, 1997
Appl. No.:
8/912539
Inventors:
Curtis Lee Cornils - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1214
US Classification:
713200
Abstract:
A method allows computer systems to handle different classes of data that are not allowed to intermingle. The method ensures that elements of the computer system not associated with a given class of data could not read from or write to the system bus while data of a different class is being transported across the system bus (10). At the same time, the method ensures that the elements of the computer system that are associated with the given class of data being transported across the bus 10 are given access to the bus (10) and the data. This is accomplished by using a single bus (10), controlling system element access to the bus with transceivers (21-31). The transceivers (21-31) are turned on or off by signals derived from system knowledge of the class of data allowed to be read or written by each system element and hence the class of data on the bus (10).

Programmable Bridging Apparatus To Connect Multiple Networks Of Different Protocols

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US Patent:
62692526, Jul 31, 2001
Filed:
May 27, 1998
Appl. No.:
9/085685
Inventors:
William Joseph Hutchings - Scottsdale AZ
Lee Silverthorn - Paradise Valley AZ
Curtis L. Cornils - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04B 136
US Classification:
455552
Abstract:
A bridging apparatus (10) for use in bridging a plurality of external communications networks (20a-20n) includes a plurality of network interfaces (12) and a bridge (14). The individual interfaces within the plurality of network interfaces (12) are each capable of converting signals between a signal format used by an associated external communications network and a common signal format supported by the bridge (14). The bridge (14) establishes at least one bridge connection between network interfaces according to a predetermined bridging function. The bridge (14) includes a digital processor having an associated memory for storing one or more bridging programs. The digital processor executes at least one of the bridging programs in order to implement the desired bridging function.
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Curtis L Cornils from Chandler, AZ, age ~70 Get Report