Search

Colin S Whelan

from Andover, MA
Age ~50
Get Report
Related to:
Sarah Long, 34Joan Y Whelan, 42Meghan Mckinsey, 36Mary Whelan, 88
Connected to:
Alana G Whelan, 26Allan C Whelan, 83Angel Whelan, 32Bernadette A Whelan, 66Brandon M Whelan, 38Brian S Whelan, 54Bride M Whelan, 87Carmen C Whelan, 34Cathal Whelan, 56Cathie A Whelan, 46

Colin Whelan Phones & Addresses

  • 1 Winterberry Ln, Andover, MA 01810 (781) 424-5687
  • 373 Highland Ave, Somerville, MA 02144 (617) 776-9720
  • 13 Cottage Ave, Arlington, MA 02474 (781) 646-8518
  • 2 Legion Rd, Weston, MA 02493
  • 16 Myrtle Ave, Wakefield, MA 01880 (781) 587-0095

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Business Records

Name / Title
Company / Classification
Phones & Addresses
Colin Whelan
Dir. Fleet Ops.
Zeemac Vehicle Lease Ltd
Zephyr Enterprises Ltd.. Zephyr Enterprises Ltd
Truck Renting & Leasing. Leasing Service. Automobile Renting. Automobile Leasing. Automobile Dealers-Used Cars. Automobile Repairing & Service
2293 Douglas Rd, Burnaby, BC V5C 5A9
(604) 298-8789, (604) 291-7330
Colin Whelan
Dir. Fleet Ops.
Zeemac Vehicle Lease Ltd
Truck Renting & Leasing · Leasing Service · Automobile Renting · Automobile Leasing · Automobile Dealers-Used Cars · Automobile Repairing & Service
(604) 298-8789, (604) 291-7330
Colin Whelan
Principal
Whelan
Business Services at Non-Commercial Site
1 Winterberry Ln, Andover, MA 01810

Publications

Us Patents

Method Of Forming A Self-Aligned, Selectively Etched, Double Recess High Electron Mobility Transistor

View page
US Patent:
6838325, Jan 4, 2005
Filed:
Oct 24, 2002
Appl. No.:
10/279358
Inventors:
Colin S. Whelan - Wakefield MA, US
Elsa K. Tong - Wayland MA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H01L 218252
US Classification:
438172, 438174, 438571, 438704
Abstract:
A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer. Next, a second wet chemical etch is brought into contact with structure etched by the first wet chemical etch.

Sulfide Encapsulation Passivation Technique

View page
US Patent:
6924218, Aug 2, 2005
Filed:
Dec 17, 2002
Appl. No.:
10/321310
Inventors:
Philbert Francis Marsh - Andover MA, US
Colin S. Whelan - Wakefield MA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H01L021/44
US Classification:
438570, 438572, 438 92
Abstract:
A method for passivating a III-V material Schottky layer of a field effect transistor. The transistor has a gate electrode in Schottky contact with a gate electrode contact region of the Schottky layer. The gate electrode is adapted to control a flow of carriers between a source electrode of the transistor and a drain electrode of such tarnsistor. The transistor has exposed surface portions of the Schottky layer beween the source electrode and the drain electrode adjacent to the gate electrode contact region of the Schottky layer. The method includes removing organic contamination from the exposed surface portions of the Schottky layer using a oxygen plasma. The contamination removed surface portions of the Schottky layer are exposed to a solution of ammonium sulfide and NHOH. After removal of the solution, the exposed regions are dried in a nitrogen enviroment. A layer of passivating material is deposited over the dried surface portions.

Photodiode Passivation Technique

View page
US Patent:
7030032, Apr 18, 2006
Filed:
May 13, 2003
Appl. No.:
10/437095
Inventors:
Philbert Francis Marsh - Andover MA, US
Colin Steven Whelan - Wakefield MA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H01L 21/302
US Classification:
438745, 438754, 257444
Abstract:
A method for passivating a photodiode so as to reduce dark current, I, due to the exposed semiconductor material on the sidewall of the device. The method includes etching away sidewall surface damage using a succinic acid-hydrogen peroxide based sidewall etch. This is followed by a subsequent hydrochloric acid (HCl)-based surface treatment which completes the surface treatment and reduces the dark current I. Finally, a polymer coating of benzocyclobutene (BCB) is applied after the surface treatment to stabilize the surface and prevent oxidation and contamination which would otherwise raise the dark current were the diodes left with no coating. The BCB is then etched away from the contact pad areas to allow wirebonding and other forms of electrical contact to the diodes. Such method effectively stabilizes the etched surfaces of photodiodes resulting in significantly reduced and stable dark current.

Method For Designing Input Circuitry For Transistor Power Amplifier

View page
US Patent:
7528649, May 5, 2009
Filed:
Sep 7, 2007
Appl. No.:
11/851418
Inventors:
Colin S. Whelan - Wakefield MA, US
Raghu Mallavarpu - Boxborough MA, US
Matthew C. Tyhach - Medford MA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
G01R 19/00
US Classification:
330 2, 330129
Abstract:
A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

Input Circuitry For Transistor Power Amplifier And Method For Designing Such Circuitry

View page
US Patent:
7609115, Oct 27, 2009
Filed:
Sep 7, 2007
Appl. No.:
11/851425
Inventors:
Colin S. Whelan - Wakefield MA, US
John C. Tremblay - Lancaster MA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H03F 3/191
US Classification:
330302, 330305
Abstract:
A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

Method And Structure For Reducing Cracks In A Dielectric Layer In Contact With Metal

View page
US Patent:
7863665, Jan 4, 2011
Filed:
Mar 29, 2007
Appl. No.:
11/693365
Inventors:
Barry J. Liles - Westborough MA, US
Colin S. Whelan - Wakefield MA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H01L 27/108
H01L 29/94
US Classification:
257303, 257 68, 257 71, 257296, 257306, 257906, 257E21008, 257E27048, 257E27092, 257E29346, 438239, 438386, 438393, 438396
Abstract:
A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.

Split-Channel High Electron Mobility Transistor (Hemt) Device

View page
US Patent:
20040262632, Dec 30, 2004
Filed:
Jun 26, 2003
Appl. No.:
10/606820
Inventors:
Philbert Marsh - Andover MA, US
Colin Whelan - Wakefield MA, US
William Hoke - Wayland MA, US
International Classification:
H01L031/0328
H01L031/072
US Classification:
257/194000, 257/192000, 257/195000
Abstract:
A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InGaAs lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an InGaAs upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the InGaAs upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.

Frequency Selective Limiter

View page
US Patent:
20150130564, May 14, 2015
Filed:
Nov 12, 2013
Appl. No.:
14/077909
Inventors:
- Waltham MA, US
Francois Y. Colomb - Westford MA, US
Robert E. Leoni - Somerville MA, US
Colin S. Whelan - Wakefield MA, US
Traugott Carl Ludwig Gerhard Soliner - Winchester MA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H01P 9/02
H01P 1/203
H01P 1/22
H01P 9/00
US Classification:
333162, 333161, 333 81 A
Abstract:
A selective frequency limiter having a magnetic material and a slow wave structure disposed to magnetically couple a magnetic field, produced by electromagnetic energy propagating through the slow wave structure, into the magnetic material.
Control profile
Colin S Whelan from Andover, MA, age ~50 Get Report