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Chun Hao Chen

from San Jose, CA
Age ~45

Chun Chen Phones & Addresses

  • 1089 Mountain Shadows Rd, San Jose, CA 95120
  • Highlands Ranch, CO
  • Centennial, CO
  • Englewood, CO
  • Newark, CA
  • Fremont, CA
  • Morgan Hill, CA

Professional Records

Medicine Doctors

Chun Chen Photo 1

Chun W. Chen

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Specialties:
Radiology
Work:
Bay Radiology Associates PL
527 N Palo Alto Ave, Panama City, FL 32401
(850) 763-2451 (phone), (850) 747-4907 (fax)
Education:
Medical School
Tulane University School of Medicine
Graduated: 1999
Procedures:
Breast Biopsy
Conditions:
Breast Disorders
Malignant Neoplasm of Colon
Malignant Neoplasm of Esophagus
Malignant Neoplasm of Female Breast
Languages:
English
Description:
Dr. Chen graduated from the Tulane University School of Medicine in 1999. He works in Panama City, FL and specializes in Radiology. Dr. Chen is affiliated with Gulf Coast Regional Medical Center.
Chun Chen Photo 2

Chun T. Chen

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Specialties:
Family Medicine
Work:
Roseland Medical Center
11416 S Michigan Ave, Chicago, IL 60628
(773) 821-1414 (phone), (773) 821-1817 (fax)
Education:
Medical School
China Med Coll, Taichung, Taiwan (244 05 Eff 1/1971)
Graduated: 1967
Conditions:
Acute Bronchitis
Acute Sinusitis
Acute Upper Respiratory Tract Infections
Allergic Rhinitis
Anxiety Phobic Disorders
Languages:
English
Spanish
Description:
Dr. Chen graduated from the China Med Coll, Taichung, Taiwan (244 05 Eff 1/1971) in 1967. He works in Chicago, IL and specializes in Family Medicine. Dr. Chen is affiliated with Alexian Brothers Medical Center and Amita Health La GrangeHospital.
Chun Chen Photo 3

Chun Chen

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Specialties:
Internal Medicine
Work:
Chun Chen MD
278 E Main St STE A, Smithtown, NY 11787
(631) 366-4550 (phone)
Education:
Medical School
Shanghai Med Univ, Shanghai First Med Univ, Shanghai, China
Graduated: 1994
Languages:
Chinese
English
Description:
Dr. Chen graduated from the Shanghai Med Univ, Shanghai First Med Univ, Shanghai, China in 1994. She works in Smithtown, NY and specializes in Internal Medicine. Dr. Chen is affiliated with Saint Catherine Of Siena Medical Center.
Chun Chen Photo 4

Chun M. Chen

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Specialties:
Anesthesiology
Work:
Minsheng Pain Management & Anesthesia
3916 Prince St APT 6A, Flushing, NY 11354
(718) 321-8066 (phone), (718) 559-6965 (fax)
Education:
Medical School
Sun Yat Sen Univ of Med Sci, Guangzhou, China (242 21 Pr 1/71)
Graduated: 1983
Languages:
English
Description:
Dr. Chen graduated from the Sun Yat Sen Univ of Med Sci, Guangzhou, China (242 21 Pr 1/71) in 1983. He works in Flushing, NY and specializes in Anesthesiology.
Chun Chen Photo 5

Chun Tong Chen

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Specialties:
Family Medicine
General Practice
Surgery
Education:
China Medical University (1967)
Chun Chen Photo 6

Chun Ming Chen

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Specialties:
Anesthesiology
Pain Medicine
Neurological Surgery
Neurology
Pain Medicine
Pain Medicine
Education:
Sun Yat-Sen University (1983)
Chun Chen Photo 7

Chun Ter Chen

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Specialties:
Anesthesiology
Education:
Chung Shan Medical University (1971)

Lawyers & Attorneys

Chun Chen Photo 8

Chun Chen - Lawyer

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Address:
Broad & Bright, Shanghai Office
Licenses:
New York - Currently registered 2011
Education:
New York University School of Law

Business Records

Name / Title
Company / Classification
Phones & Addresses
Chun Ya Chen
President
BENEFIT TOMORROW
1076 Johnson Ave, San Jose, CA 95129
Chun Ya Chen
President
NUTREND, INC
Nonclassifiable Establishments
945 Arikara Dr, Fremont, CA 94539
Chun Chich Chen
President
PACIFIC QUEST, INC
Whol Toys/Hobby Goods Whol Farm Supplies Whol Commercial Equip Whol Sporting Goods/Supp
1141 Ringwood Ct #130, San Jose, CA 95131
(408) 955-9804
Chun Y. Chen
Managing
Ctjg Family Investment Holding LLC
Real Estate Holding
19149 Allendale Ave, Saratoga, CA 95070
Chun Ya Chen
Benefit Tomorrow Associates LLC
Rental Real Estate - Single Family Resid
1000 Avondale St, San Jose, CA 95129
Chun Feng Chen
MMCHEN, LLC
Chun Ying Chen
WASABI HOUSE OF COPLEY LLC
Chun Qing Chen
DRAGON CITY USA INC

Publications

Amazon

My Doggie Diaries

My Doggie Diaries

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My name is Tiger. I was born on May 25, 2003 with 6 other brothers and sisters. My biological mom told me that my dad was a handsome Rottweiler. However, if you ask me, I think I look more like a mix of golden retriever and German Shepherd because of my golden fur and long hairy tail. Mommy, Gra...

Author

I-Chun Chen

Binding

Kindle Edition

Pages

103

Publisher

I-Chun Chen

ISBN #

10

An Investigation Of Asknshare Model Of Consumer Marketing In A Modern Metropolis : A Case Study At Fan's Cafe In Cloud Nine Shopping Mall, Shanghai (Asknshare Technical Report Cn-2013-Apr)

An Investigation of AskNshare Model of Consumer Marketing in a Modern Metropolis : A Case Study at Fan's Cafe in Cloud Nine Shopping Mall, Shanghai (AskNshare Technical Report CN-2013-Apr)

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This technical report is the product of collaboration between AskNshare, LLC, a division of Bose International Investment Fund, LLC and Shanghai Bo Chen Business Consulting Co., Ltd. AskNshare.net is a disruptive social media powered market research platform for consumer service providers. In this r...

Author

Ashoke Bose, Jiangying Zhang, Yue Yang, Sheng Xue Gu, Chun Yu Chen

Binding

Kindle Edition

Pages

21

Publisher

AskNshare, LLC

ISBN #

7

Aqualog: Asian Arowana

AQUALOG: Asian Arowana

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The Asian Arowanas (Scleropages sp.) belong to the most fascinating fish of the World. Due to their brilliant colors, their large scales, their swimming pattern and their large fins, they remind us of the ancient and mythological Dragons! Keeping these Dragon fishes at home brings luck and fits perf...

Binding

Hardcover

Pages

224

Publisher

Verlag A.C.S. GmbH

ISBN #

393602796X

EAN Code

9783936027969

ISBN #

5

Us Patents

Flash Memory Cell For High Efficiency Programming

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US Patent:
6384447, May 7, 2002
Filed:
Aug 1, 2001
Appl. No.:
09/920214
Inventors:
Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2976
US Classification:
257314, 257315, 36518518
Abstract:
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Method Of Reducing Trapped Holes Induced By Erase Operations In The Tunnel Oxide Of Flash Memory Cells

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US Patent:
6426898, Jul 30, 2002
Filed:
Mar 5, 2001
Appl. No.:
09/797682
Inventors:
Andrei Mihnea - San Jose CA
Jeffrey Kessenich - Boise ID
Chun Chen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
3651853, 438257, 438266, 36518511, 36518529, 365218, 365233
Abstract:
A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.

Flash Memory Cell For High Efficiency Programming

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US Patent:
6434045, Aug 13, 2002
Filed:
Jun 7, 2001
Appl. No.:
09/876674
Inventors:
Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 1604
US Classification:
36518518, 36518514
Abstract:
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Flash Memory Cell For High Efficiency Programming

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US Patent:
6445619, Sep 3, 2002
Filed:
Aug 1, 2001
Appl. No.:
09/920364
Inventors:
Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 1604
US Classification:
36518529, 36518514
Abstract:
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Flash Memory Cell For High Efficiency Programming

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US Patent:
6445620, Sep 3, 2002
Filed:
Aug 1, 2001
Appl. No.:
09/920465
Inventors:
Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 1604
US Classification:
36518529, 36518518
Abstract:
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Flash Memory Cell For High Efficiency Programming

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US Patent:
6449189, Sep 10, 2002
Filed:
Aug 1, 2001
Appl. No.:
09/920460
Inventors:
Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 1604
US Classification:
36518518, 36518514
Abstract:
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Method Of Reducing Trapped Holes Induced By Erase Operations In The Tunnel Oxide Of Flash Memory Cells

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US Patent:
6493280, Dec 10, 2002
Filed:
Oct 22, 2001
Appl. No.:
09/982682
Inventors:
Andrei Mihnea - San Jose CA
Jeffrey Kessenich - Boise ID
Chun Chen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365218, 36518529, 3651853, 36518528, 36518518, 36518522
Abstract:
A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.

Flash Memory Device And Method Of Erasing

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US Patent:
6563741, May 13, 2003
Filed:
Jan 30, 2001
Appl. No.:
09/772667
Inventors:
Andrei Mihnea - San Jose CA
Chun Chen - Boise ID
Paul Rudeck - Boise ID
Andrew R. Bicksler - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 1604
US Classification:
36518529, 3651853
Abstract:
A non-volatile memory device includes an improved method for erasing a block of stack-gate single transistor flash memory cells. The memory performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array. The erase pulse(s) fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block. The block convergence operation brings a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunnelling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential.
Chun Hao Chen from San Jose, CA, age ~45 Get Report