Christopher William Schuermyer

20100229061, Sep 9, 2010

Mar 5, 2010

12/718799

Friedrich HAPKE - Winsen, DE
Rene Krenz-Baath - Hamburg, DE
Andreas Glowatz - Heidenau, DE
Juergen Schloeffel - Buchholz/Sproetze, DE
Peter Weseloh - Rosengarten/Westerhof, DE
Michael Wittke - Pinneberg, DE
Mark A. Kassab - Wilsonville OR, US
Christopher W. Schuermyer - Happy Valley OR, US

G01R 31/3177
G06F 11/25

714740, 714E11155

Cell-aware fault models directly address layout-based intra-cell defects. They are created by performing analog simulations on the transistor-level netlist of a library cell and then by library view synthesis. The cell-aware fault models may be used to generate cell-aware test patterns, which usually have higher defect coverage than those generated by conventional ATPG techniques. The cell-aware fault models may also be used to improve defect coverage of a set of test patterns generated by conventional ATPG techniques.

20130219216, Aug 22, 2013

Feb 15, 2013

13/769230

MENTOR GRAPHICS CORPORATION - , US
Christopher W. Schuermyer - Happy Valley OR, US

MENTOR GRAPHICS CORPORATION - Wilsonville OR

G06F 11/07

714 26

Aspects of the invention relate to techniques for classifying memory failure bitmaps using both rule-based classification and artificial neural network-based classification methods. The rule-based classification method employs classification rules comprising those for global failure patterns. The artificial neural network-based classification method classifies local failure patterns. One of the artificial neural network models is the Kohonen self-organizing map model. The input vector for a failure pattern may contain four elements: pattern aspect ratio, failing bit ratio, dominant failing column number and dominant failing row number.

20140059511, Feb 27, 2014

Aug 22, 2013

13/973998

Christopher Schuermyer - Happy Valley OR, US
Jonathan J. Muirhead - Tigard OR, US
Leo Chang - Taichung City, TW

Mentor Graphics Corporation - Wilsonville OR

G06F 17/50

716136

Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.

20080052029, Feb 28, 2008

Aug 24, 2006

11/466846

Robert B. Benware - Clackamas OR, US
Mark A. Ward - West Linn OR, US
Christopher W. Schuermyer - Troutdale OR, US

LSI LOGIC CORPORATION - Milpitas CA

G06F 19/00
G06F 17/50

702117, 716 1, 702108

A method of retrieving a unique, repeatable identification value from an integrated circuit by identifying a plurality of state elements within the integrated circuit, where the state elements are part of standard functional circuitry within the integrated circuit, and are not part of a specialized circuit designed to primarily produce the unique, repeatable identification value, performing an initializing process on the state elements to bring the state elements to repeatable states, where the repeatable states of different state elements are dependent at least in part on differences between the different state elements, reading the repeatable states on the state elements, and joining the repeatable states into a binary number as the unique, repeatable identification value.

20170103158, Apr 13, 2017

Sep 12, 2016

15/263014

- Wilsonville OR, US
Christopher Schuermyer - Happy Valley OR, US
Jonathan J. Muirhead - Tigard OR, US
Chen-Yi Chang - Taichung City, TW

Mentor Graphics Corporation - Wilsonville OR

G06F 17/50

Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.