Ching-Ping Chou

8473661, Jun 25, 2013

Aug 14, 2009

12/541868

Ching-Ping Chou - Saratoga CA, US
Darren Kwan - Menlo Park CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 13/00
G06F 13/36
G06F 15/173
G06F 15/177

710242, 709222, 709224, 710311, 710316

A method and system for providing multi-process protection using direct memory mapped control registers is disclosed. According to one embodiment, a computer-implemented method provides a set of control registers for each execution unit of a plurality of execution units in a controller switch. The controller switch facilitates communication between a host system and one or more devices connected to a plurality of device ports of the controller switch. A device driver is provided to allow users' processes to access the controller switch and to grant exclusive access to each execution unit of the plurality of execution units. A first access request to access an execution unit of the plurality of execution units is received from a first process. A set of direct accessible addresses to the set of control registers of the execution unit is allocated, and the first process is granted to exclusive access the execution unit until the first process release the exclusive access to the execution unit. A second access request to access the execution unit received from a second process is denied by checking the assignment of the set of direct accessible addresses to the set of control registers of the execution unit while the first process retains exclusive access to the execution unit.

20110041105, Feb 17, 2011

Aug 14, 2009

12/541864

Ching-Ping Chou - Saratoga CA, US
Su-Jen Hwang - Los Altos CA, US

G06F 17/50

716106

A method and system for facilitating communication between a host system and one or more hardware-based functional verification systems. The one or more hardware-based functional verification systems verify the functionality of electronic circuit designs. A controller switch comprises a host interface connecting to a host system, and a plurality of device ports. Each device port connects to a hardware emulator. The controller switch further comprises a plurality of direct memory access (DMA) engines and a plurality of execution units. An execution unit comprises an instruction cache and memory storing at least one DMA instruction and at least one address for performing a software instruction and a plurality of execution unit registers.

20210150110, May 20, 2021

Jan 28, 2021

17/161574

- Mountain View CA, US
Ching-Ping Chou - Mountain View CA, US
Jean-Philippe Colrat - Mountain View CA, US
Luc Francois Vidal - Mountain View CA, US
Arnold Mbotchak - Mountain View CA, US

G06F 30/331

A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.

20180121573, May 3, 2018

Oct 31, 2017

15/798832

- Mountain View CA, US
Ching-Ping Chou - Saratoga CA, US

G06F 17/50

A computer-aided method for configuring a hardware verification system is presented. The method includes receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system, and transforming, using the computer, the first data into a second data representative of a second design. The second design includes a functionality of the first design, and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design when the hardware verification system is configured with the second data and run. The first circuit is programmable without reconfiguring the second design.