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Charles Frank Machala

from Dallas, TX
Age ~44
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Related to:
Kimberly Machala, 38Susan Trimm Machala, 63Andrea M Rauch, 58Wenhsing Cheng, 50Lori Jenson, 63Liang L Jenq, 53Pang Cheng, 83Wei Cheng, 39
Connected to:
Brian A Machala, 47Dariusz S Machala, 48Helen J Machala, 80Peter J Machala, 31Andrea R Machalek, 61Ewa M Machalek, 68Gary J Machalec, 74Gregory L Machalec, 32Kenneth Machalek, 63Kevin J Machalek, 61

Charles Machala Phones & Addresses

  • Dallas, TX
  • Grand Prairie, TX
  • Plano, TX

Resumes

Resumes

Charles Machala Photo 1

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Location:
Dallas, TX
Industry:
Real Estate
Work:

Manager
Charles Machala Photo 2

Charles Machala

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Publications

Us Patents

Method For Improving Transistor Leakage Current Uniformity

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US Patent:
20050130432, Jun 16, 2005
Filed:
Dec 11, 2003
Appl. No.:
10/735229
Inventors:
Charles Machala - Plano TX, US
International Classification:
H01L021/311
US Classification:
438694000
Abstract:
Methods are described for fabricating semiconductor devices and transistors thereof, in which a patterned gate length is measured and offset spacers are formed along the sides of the patterned gate prior to drain extension implants, wherein the offset spacer width is controlled according to the measured gate length. This facilitates consistent control over transistor channel length despite variability in the patterned gate length dimension from wafer to wafer and/or from lot to lot.

Method And System For Optimizing A Transistor Model

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US Patent:
54249643, Jun 13, 1995
Filed:
Apr 13, 1993
Appl. No.:
8/046532
Inventors:
Charles F. Machala - Dallas TX
James E. Flowers - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1750
US Classification:
364578
Abstract:
A modeling system 10 comprises a central processing unit 12 coupled to an arithmetic logic unit 16. A device testing system 18 is used to empirically analyze the operational characteristics of a transistor to be modeled by the system 10. A set of parameter values are stored in a memory circuit 14 coupled to central processing unit 12. An input and display system 20 is used to interact with the central processing unit 12. The central processing unit 12 uses the arithmetic logic unit 16 to calculate an objective function which is essentially a measure of the error between the measured values of operating variables of the device to be modeled and theoretical values of the operating variables calculated using initial guesses of modeling parameters. The objective function is minimized by calculating the gradient of the objection function to obtain a next guess point with its associated parameter values. If one of the parameter values for the next guess point violates a constraint on that parameter value, the gradient of the objective function is recalculated ignoring the particular parameter.

Optimization System

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US Patent:
52572005, Oct 26, 1993
Filed:
Dec 8, 1992
Appl. No.:
7/988385
Inventors:
Charles F. Machala - Dallas TX
James E. Flowers - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1520
US Classification:
364488
Abstract:
A modeling system 10 comprises a central processing unit 12 coupled to an arithmetic logic unit 16. A device testing system 18 is used to empirically analyze the operational characteristics of a transistor to be modeled by the system 10. A set of parameter values are stored in a memory circuit 14 coupled to central processing unit 12. An input and display system 20 is used to interact with the central processing unit 12. The central processing unit 12 uses the arithmetic logic unit 16 to calculate an objective function which is essentially a measure of the error between the measured values of operating variables of the device to be modeled and theoretical values of the operating variables calculated using initial guesses of modeling parameters. The objective function is minimized by calculating the gradient of the objection function to obtain a next guess point with its associated parameter values. If one of the parameter values for the next guess point violates a constraint on that parameter value, the gradient of the objective function is recalculated ignoring the particular parameter.

Optimization System

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US Patent:
52650286, Nov 23, 1993
Filed:
Dec 21, 1990
Appl. No.:
7/632280
Inventors:
Charles F. Machala III - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1520
US Classification:
364488
Abstract:
A modeling system 10 comprises a central processing unit 12 coupled to an arithmetic logic unit 16. A device testing system 18 is used to imperically analyze the operational characteristics of a transistor to be modeled by the system 10. A set of parameter values are stored in a memory circuit 14 coupled to central processing unit 12. An input and display system 20 is used to interact with the central processing unit 12. The central processing unit 12 uses the arithmetic logic unit 16 to calculate an objective function which comprises a sum of a plurality of two types of terms. The first term within the objective function utilizes relative weighting with respect to the values of the remaining terms while the second type of term utilizes absolute weighting with respect to the remaining terms. Both types of terms are normalized such that they are of substantially equal significance during the calculation of the objective function. Once a minimum value of the objective function has been found, a set of final modeling parameters is output to a circuit design system 21 which utilizes the final set of modeling parameters to design circuitry comprising a plurality of transistors substantially similar to the transistor modeled by the system 10.
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Charles Frank Machala from Dallas, TX, age ~44 Get Report