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Burke B Baumann

from Phoenix, AZ
Age ~70

Burke Baumann Phones & Addresses

  • 3204 Grandview Rd, Phoenix, AZ 85053 (602) 354-5864
  • Maricopa, AZ
  • 9604 53Rd Ave, Glendale, AZ 85302

Business Records

Name / Title
Company / Classification
Phones & Addresses
Burke Baumann
Manager
BLD PROPERTIES, LLC
2328 N 52 St, Phoenix, AZ 85008
9604 N 53 Ave, Glendale, AZ 85302

Publications

Us Patents

Receive Manchester Clock Circuit

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US Patent:
47886056, Nov 29, 1988
Filed:
Mar 30, 1987
Appl. No.:
7/031957
Inventors:
Robert L. Spiesman - Phoenix AZ
Burke B. Baumann - Glendale AZ
Assignee:
Honeywell Inc. - Minneapolis MN
International Classification:
G11B 509
US Classification:
360 42
Abstract:
A circuit for producing a receive Manchester clock from serially received Manchester encoded data signals. The encoded data signals are differentiated to produce a primary clock pulse for each voltage transition of the applied signals. Each primary clock pulse is delayed a predetermined period of time to produce secondary clock pulse and each secondary clock pulse is delayed for substantially the same period of time to produce a tertiary clock pulse. The primary, secondary and tertiary clock pulses are applied to a gate which produces a receive Manchester clock pulse when a primary, secondary, or tertiary clock pulse is applied to the gate. The frequency of the receive Manchester clock is twice that of the basic frequency of the received Manchester encoded data signals.

Apparatus For Modifying Microinstructions Of A Microprogrammed Processor

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US Patent:
48253634, Apr 25, 1989
Filed:
Dec 5, 1984
Appl. No.:
6/678536
Inventors:
Burke B. Baumann - Glendale AZ
Troy K. Wilson - Phoenix AZ
Assignee:
Honeywell Inc. - Minneapolis MN
International Classification:
G06F 922
US Classification:
364200
Abstract:
A controller of a microprocessor includes a control store for storing microinstructions. A programmable logic array (PLA), enabled when a predetermined macroinstruction type is to be executed, translated the operand field of the macroinstruction into information bits which are used to modify the microinstruction as it is being fetched from the control store. The bits of the microinstruction which are changeable are coupled from the control store to a first input of a multiplexer. The output of the PLA is coupled to a second input of the multiplexer. A select signal for the multiplexer is generated when the predetermined instruction type is to be excuted, thereby effecting a modification of the fetched microinstruction, and yielding a modification to the basic operation of the macroinstruction.

Apparatus For Arbitrating Between A Plurality Of Requestor Elements

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US Patent:
46125426, Sep 16, 1986
Filed:
Dec 20, 1984
Appl. No.:
6/684312
Inventors:
William J. Pantry - Portland OR
Burke B. Baumann - Glendale AZ
Assignee:
Honeywell Inc. - Phoenix AZ
International Classification:
H04Q 900
US Classification:
3408255
Abstract:
An arbitration circuit comprises a plurality of enabling elements which determines when predetermined conditions exist to transmit a request signal. A first gate combines transmitted request signals to generate a combined request signal. A plurality of first latches, each first latch having a sequential priority order and operatively connected to a corresponding enabling element, and further connected to the output of the first gate, generates an enable and a disable signal. A plurality of second gates is included, each second gate is operatively connected to the first gate to receive the combined request signal, and each second gate operatively connected to the corresponding first latch to receive the enable signal. Further, each of the second gates is operatively connected to each first latch having a higher sequential priority to receive the disable signal from each of the higher sequential priority first latches, each of the second gates generating a select control signal corresponding to the request signal selected by the arbitration circuit, thereby permitting a requestor access to the bus.

Dual Bus System

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US Patent:
49823213, Jan 1, 1991
Filed:
Oct 23, 1987
Appl. No.:
7/113418
Inventors:
William J. Pantry - Portland OR
Burke B. Baumann - Glendale AZ
Assignee:
Honeywell Inc. - Minneapolis MN
International Classification:
G06F 1300
US Classification:
364200
Abstract:
The data processing system, has at least one memory unit operatively connected to a memory bus, and further has an input/output (I/O) bus controller for interfacing at least one peripheral device to the data processing system. The data processing system comprises a first bus which provides a first transmission medium between the peripheral device and the memory bus. A second bus, provides a second transmission medium between a CPU and the memory bus. A logic element, interposed between the first and second bus, and the memory bus, interfaces the first and second bus to the memory bus in response to request signals from the first and second bus.
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