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Brian P Verstegen

from Santa Cruz, CA
Age ~75
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Also known as:
Brian Living Verstegen, Brian Te Verstegen, Brian C Verstegen, Brian Verstegen Revocabl, Brian Verstegan, Kate Verstegan
Phone and address:
124 Berkshire Ave, Santa Cruz, CA 95060
Related to:
Laurina Elizabeth Marasco, 66Mark E Chase, 69Justin E Chase, 39Kelly Verstegen, 35Kaitlin A Verstegen, 36Benjamin E Verstegen, 39Andrea Verstegen, 36Elizabeth E Chase, 68
Connected to:
Adam J Versteegen, 45Jon F Versteeg, 60Leo A Versteeg, 105Peter E Verstegen, 76Ray E Versteeg, 58Ron R Versteeg, 75Saskia H Versteeg, 32Todd A Versteeg, 47Victoria M Versteeg, 32Andrew Verstein, 40

Brian Verstegen Phones & Addresses

  • 124 Berkshire Ave, Santa Cruz, CA 95060
  • 757 Holbrook Pl, Sunnyvale, CA 94087 (408) 737-9218
  • 860 Iowa Ave, Sunnyvale, CA 94086 (408) 730-4186 (408) 737-9218
  • 920 Remington Ct, Sunnyvale, CA 94087 (408) 730-4186 (408) 737-9218
  • Santa Clara, CA
  • Lovettsville, VA
  • 860 W Iowa Ave, Sunnyvale, CA 94086

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Emails

b***[email protected]

Publications

Us Patents

Modular Computer System And Method

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US Patent:
20020166010, Nov 7, 2002
Filed:
May 1, 2001
Appl. No.:
09/846807
Inventors:
Erich Selna - Sunnyvale CA, US
Leesa Noujeim - Sunnyvale CA, US
Brian Verstegen - Sunnyvale CA, US
Assignee:
Sun Microsystems, Inc
International Classification:
G06F013/00
US Classification:
710/100000
Abstract:
A computer system includes a primary chassis and a secondary chassis. The computer system further includes a primary device having a bus for carrying electrical signals and an external device having a bus for carrying electrical signals. The primary device is disposed in a primary chassis and the external device is disposed in the secondary chassis. The external device is directly electrically interconnected with the primary device so that the electrical signals carried on the primary device bus are transmitted to the secondary bus and the electrical signals carried on the external device bus are transmitted to the primary device bus. A method capable of sharing electrical signals includes transmitting a first electrical signal over a bus of a primary device disposed in a primary chassis and receiving the first electrical signal over a bus of an external device disposed in a secondary chassis.

Method And Apparatus For Interfacing A Bus With An External Device

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US Patent:
20020166019, Nov 7, 2002
Filed:
May 1, 2001
Appl. No.:
09/846959
Inventors:
Leesa Noujeim - Sunnyvale CA, US
Brian Verstegen - Sunnyvale CA, US
Erich Selna - Sunnyvale CA, US
International Classification:
G06F013/38
US Classification:
710/301000
Abstract:
A method for controlling a bus is provided. In particular, an external device may be interfaced with a bus internal to a computer system. The method involves detecting when a device is coupled to the bus, and driving signals onto the bus in response to detecting the device being coupled to the bus. Alternatively, when the external device is not coupled to the bus, the signals are blocked, disabled, or otherwise prevented from being delivered onto the bus.

Sleep Mode Refresh Apparatus

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US Patent:
52476553, Sep 21, 1993
Filed:
Nov 7, 1989
Appl. No.:
7/432680
Inventors:
Rashid N. Khan - Cupertino CA
Cheng Chen - San Jose CA
Chien-Feng Cheng - Cupertino CA
Brian Verstegen - Sunnyvale CA
Aurav Gollabinnie - San Jose CA
Assignee:
Chips and Technologies, Inc. - San Jose CA
International Classification:
G11C 100
US Classification:
395550
Abstract:
A circuit for waking a microprocessor from a sleep mode and providing it with its microprocessor clock long enough for a refresh, direct memory access (DMA) or master cycle operation to be done by external circuitry. The clock signal is then removed from the microprocessor to put it back into the sleep mode, thereby conserving energy. A hold signal is provided to the microprocessor to cause the microprocessor outputs to be put into a tri-state, high impedance condition, and thus relinquish control of the external bus to the external refreshing circuitry.

Interrupt-Generating Keyboard Scanner Using An Image Ram

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US Patent:
53865847, Jan 31, 1995
Filed:
Oct 5, 1993
Appl. No.:
8/132125
Inventors:
Brian Verstegen - Sunnyvale CA
Lance King - Newark CA
George A. Vlantis - Sunnyvale CA
Assignee:
Chips and Technologies, Inc. - San Jose CA
International Classification:
G06F 302
US Classification:
391800
Abstract:
A system for assisting the scanning of a keyboard associated with a personal computer. The system comprises a logic circuit which interacts with the microcontroller and the keyboard to reduce power consumption by the personal computer as well as freeing the microcontroller to do other tasks. The logic circuit "interrupts" the microcontroller whenever keyboard activity is detected. An image RAM stores a pattern of current key closures to be compared in subsequent keyboard scans. A subsequent miscompare between the keyboard and the Image RAM indicates that keyboard activity has occurred. When no keys are pressed, scanning may be stopped. Any key closure will then generate an interrupt, and the microcontroller will restart scanning.

Read Only Memory Character Generator System

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US Patent:
41875524, Feb 5, 1980
Filed:
Sep 20, 1978
Appl. No.:
5/944082
Inventors:
Brian P. Verstegen - Sunnyvale CA
Assignee:
Durango Systems, Inc. - Cupertino CA
International Classification:
B41J 350
US Classification:
364900
Abstract:
A read only memory character generator system for generating dot print characters of a given font within a nine-column-by-nine-row dot matrix comprising a read only memory having a storage capacity of one byte per row of memory, the memory having a first memory means, a second memory means and a third memory means with the first memory means having nine memory row locations of memory storage devices for each character of the font to be printed, the memory storage devices at each successive row for each character being burned in pursuant to the dot matrix pattern for successive columns of dots of not more than eight rows for that given column of that given character, the second memory means having one memory row location of memory storage devices for each character of the font to be printed with the storage devices at each location being burned in pursuant to the dot matrix pattern of the remaining columns of the ninth row dot matrix pattern for not more than six columns of dots for the ninth row of one of said characters and a binary code representation for the dot matrix pattern for that particular character, and said third memory means having one memory row location of memory storage devices for each of said differing binary code representations with the storage devices at each location being burned in pursuant to the dot matrix pattern representation of one of said binary-coded representations.
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Brian P Verstegen from Santa Cruz, CA, age ~75 Get Report