Brian J Goolsby

7208424, Apr 24, 2007

Sep 17, 2004

10/943383

Tab A. Stephens - Austin TX, US
Brian J. Goolsby - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/302
H01L 21/461

438720, 438734, 438963, 257E2131, 257E21311, 257E21313

A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.

7238561, Jul 3, 2007

Aug 2, 2005

11/195510

Da Zhang - Austin TX, US
Veer Dhandapani - Round Rock TX, US
Brian Goolsby - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/336

438197, 438296, 438481, 438E21431

A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate () with a gate structure () disposed thereon, wherein the gate structure comprises a gate electrode () and at least one spacer structure (), and wherein the substrate comprises a first semiconductor material. A first trench () is created in the substrate adjacent to the gate structure through the use of a first etch. The gate electrode is then etched with a second etch. Preferably, the minimum cumulative reduction in thickness of the gate electrode from the first and second etches is d, the maximum depth of the first and second trenches after the first and second etches is d, and d≧d.

7265004, Sep 4, 2007

Nov 14, 2005

11/273092

Brian J. Goolsby - Austin TX, US
Linda B. McCormick - Dripping Springs TX, US
Colita M. Parker - Austin TX, US
Mariam G. Sadaka - Austin TX, US
Victor H. Vartanian - Dripping Springs TX, US
Ted R. White - Austin TX, US
Melissa O. Zavala - Pflugerville TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/84

438151, 438154, 438285, 257E21561

An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e. g. , germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

7402476, Jul 22, 2008

Jun 15, 2005

11/152931

Marius K. Orlowski - Austin TX, US
Brian J. Goolsby - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/8238
H01L 21/336

438199, 438300, 257E21632, 257E21668

An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.

7566623, Jul 28, 2009

Feb 2, 2007

11/670833

Leo Mathew - Austin TX, US
Brian J. Goolsby - Austin TX, US
Tab A. Stephens - Buda TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/336

438283, 257365

An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.

7737496, Jun 15, 2010

Aug 10, 2007

11/836844

Brian J. Goolsby - Austin TX, US
Linda B. McCormick - Dripping Springs TX, US
Colita M. Parker - Austin TX, US
Mariam G. Sadaka - Austin TX, US
Victor H. Vartanian - Dripping Springs TX, US
Ted R. White - Austin TX, US
Melissa O. Zavala - Pflugerville TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/84

257347, 257E21561

An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e. g. , germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

7821067, Oct 26, 2010

Aug 10, 2007

11/836844

Brian J. Goolsby - Austin TX, US
Linda B. McCormick - Dripping Springs TX, US
Colita M. Parker - Austin TX, US
Mariam G. Sadaka - Austin TX, US
Victor H. Vartanian - Dripping Springs TX, US
Ted R. White - Austin TX, US
Melissa O. Zavala - Pflugerville TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/84

257347, 257E21561

An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e. g. , germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

7361561, Apr 22, 2008

Jun 24, 2005

11/166138

Brian J. Goolsby - Austin TX, US
Bruce E. White - Round Rock TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/336

438287, 257E21625

A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to form a sidewall spacer on the polysilicon gate and to re-expose the previously exposed portion of the metal layer. The re-exposed metal layer is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer. Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate but for the protection provided by the sidewall spacer. After the re-exposed metal has been removed, a transistor is formed in which the metal layer sets the work function of the gate of the transistor.