Resumes
Resumes
Bret Rothenberg Phones & Addresses
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Carmel, CA
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Portola Valley, CA
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974 Mercedes Ave, Los Altos, CA 94022 (650) 947-9238
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536 El Monte Ave, Los Altos, CA 94022 (650) 947-9238
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666 El Monte Ave, Los Altos Hills, CA 94022 (650) 947-9238
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Emerald Hills, CA
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San Mateo, CA
Publications
Us Patents
Automatic Burst Mode I/Q Gain And I/Q Phase Calibration Using Packet Based-Fixed Correction Coefficients
View pageUS Patent:
6940930, Sep 6, 2005
Filed:
Aug 7, 2003
Appl. No.:
10/636045
Inventors:
James E. C. Brown - San Jose CA, US
Bret Rothenberg - Los Altos CA, US
Bret Rothenberg - Los Altos CA, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04L027/06
US Classification:
375343, 375316, 375147, 375322, 375326, 455296, 455313
Abstract:
A method and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. The receiver includes an IQ coefficient calculator and an IQ balancer. The IQ coefficient calculator computes a set of correction coefficients for each packet from the I and Q signals in an IQ measurement section at the front of the packet. The IQ balancer uses the correction coefficients for correcting the I/Q gain and I/Q phase errors on a packet-by-packet basis. Optionally, delay devices delay the I and Q signals so that the correction coefficients may be applied to the entire packet, or the portion of the packet in the IQ measurement section is passed through uncorrected and the correction coefficients are applied to the packet after the IQ measurement section.
Transmitter And Method Having A Low Sampling Frequency For Digital To Analog Conversion
View pageUS Patent:
6950478, Sep 27, 2005
Filed:
Aug 2, 2001
Appl. No.:
09/920881
Inventors:
Bret Rothenberg - Los Altos CA, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04L027/12
US Classification:
375295, 455 91
Abstract:
An apparatus and a method having a low sampling clock frequency for converting a digital signal having IF frequency channels to an analog IF signal. A DAC uses the sampling signal for converting the digital signal to the analog IF signal. A high-low RFLO signal generator generates an RFLO signal that is controlled to switch between a first RFLO frequency below a desired RF frequency band and a second RFLO frequency above the desired RF frequency band. The RF upconverter uses the first RFLO frequency for upconverting IF frequency channels into RF frequency channels in the lower half of the RF frequency band and uses the second RFLO frequency for upconverting the same IF frequency channels into different RF frequency channels in the upper half of the RF frequency band, thereby enabling the DAC to use a lower frequency sampling signal.
Method And Apparatus For Measuring Phase Error Of A Modulated Signal
View pageUS Patent:
7123665, Oct 17, 2006
Filed:
May 9, 2003
Appl. No.:
10/435272
Inventors:
James E. C. Brown - San Jose CA, US
Bret Rothenberg - Los Altos CA, US
Bret Rothenberg - Los Altos CA, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04L 27/12
US Classification:
375303, 375272, 375274, 375295, 375296, 375305, 455 43, 455 63, 455 671, 455113, 455115, 455126, 332126, 332127, 332162
Abstract:
A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.
Gaussian Minimum Shift Key Transmitter With Feedforward Phase Compensation
View pageUS Patent:
7123666, Oct 17, 2006
Filed:
May 9, 2003
Appl. No.:
10/435273
Inventors:
James E. C. Brown - San Jose CA, US
Bret Rothenberg - Los Altos CA, US
Chienkuo Vincent Tien - Cupertino CA, US
Bret Rothenberg - Los Altos CA, US
Chienkuo Vincent Tien - Cupertino CA, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04L 27/12
US Classification:
375303, 272274, 272295, 272296, 272305, 455 63, 455 671, 455113, 455115, 455126, 332126, 332127, 332162
Abstract:
A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.
Full Duplex Transceiver Having A Method For Immunizing Itself Against Self-Jamming
View pageUS Patent:
7155179, Dec 26, 2006
Filed:
Jul 16, 2001
Appl. No.:
09/906292
Inventors:
Bret Rothenberg - Los Altos CA, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04B 1/04
US Classification:
4551142, 455 1, 455 73, 455 78, 455 83, 455 84, 455141, 455283, 455296
Abstract:
A full-duplex transceiver using a method immunizing itself against self-jamming. The transceiver includes a receiver and a transmitter. The receiver includes a frequency immunization converter and a high pass IF filter. The transmitter transmits a TX signal. The receiver receives an RX signal and simultaneously receives a portion of the power of the TX signal as an undesired TX jamming signal. The frequency immunization converter uses the center frequency of the TX signal for downconverting the RX signal to an IF signal and simultaneously downconverting the TX jamming signal to near zero frequency. The high pass IF filter passes the IF signal and blocks the signal at near zero frequency. As a consequence of the downconversion using the TX frequency, a second LO frequency is controlled for avoiding image frequencies.
Voltage Regulator Bypass Resistance Control
View pageUS Patent:
8248044, Aug 21, 2012
Filed:
Mar 24, 2010
Appl. No.:
12/730333
Inventors:
James E. C. Brown - San Jose CA, US
Bret Rothenberg - Los Altos CA, US
Lawrence M. Burns - Los Altos CA, US
Bret Rothenberg - Los Altos CA, US
Lawrence M. Burns - Los Altos CA, US
Assignee:
R2 Semiconductor, Inc. - Sunnyvale CA
International Classification:
G05F 1/613
US Classification:
323224, 323284, 323266
Abstract:
Embodiments for at least one method and apparatus of controlling a bypass resistance of a voltage regulator are disclosed. One method includes generating a regulated output voltage based upon a switching voltage. The switching voltage is generated through controlled closing and opening of a series switch element and a shunt switch element, the series switch element and the shunt switch element being connected between voltages based on an input voltage. A control of a duty cycle of the switching voltage is provided by sensing and feeding back the regulated output voltage. The bypass resistance is controlled based on a parameter related to the duty cycle, wherein the control of the duty cycle is persistent during the control of the bypass resistance.
Voltage Regulator Bypass Resistance Control
View pageUS Patent:
8339115, Dec 25, 2012
Filed:
Jul 5, 2012
Appl. No.:
13/542572
Inventors:
James E. C. Brown - San Jose CA, US
Bret Rothenberg - Los Altos CA, US
Lawrence M. Burns - Los Altos CA, US
Bret Rothenberg - Los Altos CA, US
Lawrence M. Burns - Los Altos CA, US
Assignee:
R2 Semiconductor, Inc. - Sunnyvale CA
International Classification:
G05F 1/613
US Classification:
323224, 323284, 323266
Abstract:
Embodiments for at least one method and apparatus of controlling a bypass resistance of a voltage regulator are disclosed. One method includes generating a regulated output voltage based upon a switching voltage. The switching voltage is generated through controlled closing and opening of a series switch element and a shunt switch element, the series switch element and the shunt switch element being connected between voltages based on an input voltage. Control of a duty cycle of the switching voltage is provided by sensing and feeding back the regulated output voltage. The bypass resistance is controlled based on an integration of a difference between the duty cycle and a maximum duty cycle.
Delay Block For Controlling A Dead Time Of A Switching Voltage Regulator
View pageUS Patent:
8648583, Feb 11, 2014
Filed:
Sep 3, 2011
Appl. No.:
13/225434
Inventors:
James E. C. Brown - San Jose CA, US
Bret Rothenberg - Los Altos CA, US
Bret Rothenberg - Los Altos CA, US
Assignee:
R2 Semiconductor, Inc. - Sunnyvale CA
International Classification:
G05F 1/00
H03K 4/90
H03L 7/06
H03K 4/90
H03L 7/06
US Classification:
323282, 327136, 327149
Abstract:
Embodiments for at least one method and apparatus for controlling timing of switch control signals of a switching voltage regulator disclosed. One method includes generating a regulated output voltage based upon a switching voltage, generating the switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and controlling, by a delay block, the closing and opening of the series switch element and a shunt switch element. The delay block control includes receiving, by the delay block, a timing signal, generating a one of a series switch control signal and a shunt switch control signal by controllably delaying the timing signal with a first delay, and generating one other of the series switch control signal and the shunt switch control signal by inverting, and controllably delaying the timing signal with a second delay.