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Biagio J Pluchino

from Lagrangeville, NY
Age ~68
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Also known as:
Jane Pluchino, Biagi Pluchino, Pluchino Biagi, Pluchino Biagio, G Pluchino
Phone and address:
64 Cunningham Dr, La Grange, NY 12540
(845) 227-2297
Related to:
Angela Bergsma, 49Joseph Pluchino, 53Alfred Damaro, 55Luis Gomez, 34
Connected to:
Anthony P Pluchino, 70Elizabeth J Pluchino, 62Gail Pluchino, 69Giovanni Pluchino, 88Karen A Pluchino, 70Kristen Pluchino, 30Robert Pluchino, 44Tracy Pluchino, 48Izabela M Plucinska, 68Lisa G Plucinski, 55

Biagio Pluchino Phones & Addresses

  • 64 Cunningham Dr, Lagrangeville, NY 12540 (845) 227-2297
  • 29 Pine Tree Dr, Poughkeepsie, NY 12603 (845) 462-8041
  • Pawling, NY
  • Deer Park, NY
  • Wappingers Falls, NY

Work

Company: Ibm Position: Senior physical design engineer

Skills

Physical Design • Information Technology

Industries

Information Technology And Services

Resumes

Resumes

Biagio Pluchino Photo 1

Senior Physical Design Engineer

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Location:
64 Cunningham Dr, Lagrangeville, NY 12540
Industry:
Information Technology And Services
Work:
Ibm
Senior Physical Design Engineer
Ibm
Integrator
Skills:
Physical Design
Information Technology

Publications

Us Patents

System For Improving A Logic Circuit And Associated Methods

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US Patent:
7895539, Feb 22, 2011
Filed:
Oct 17, 2007
Appl. No.:
11/873919
Inventors:
Christopher Carney - Red Hook NY, US
Jose Luis Pontes Correia Neves - Poughkeepsie NY, US
Biagio Pluchino - Lagrangeville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 2, 716 6, 716 7
Abstract:
A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net.

Multi-Emitter Bicmos Logic Circuit Family With Superior Performance

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US Patent:
51665522, Nov 24, 1992
Filed:
Mar 8, 1991
Appl. No.:
7/659404
Inventors:
Anthony G. Aipperspach - Rochester MN
Gerard Boudon - Mennecy, FR
Allan H. Dansky - Poughkeepsie NY
Pierre Mollier - Boissise Le Roi, FR
Ieng Ong - Anthony, FR
Nghia Phan - Rochester MN
Biagio Pluchino - Poughkeepsie NY
Steven J. Zier - Hopewell Junction NY
Adrian Zuckerman - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 1704
US Classification:
307446
Abstract:
A multi emitter multi input BICMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. According to one embodiment of the present invention, the pull up block (32) is comprised of a plurality of identical basic cells, each comprised of a CMOS inverter (C31, C32) driving an NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the inputs of the inverters (C31, C32), and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All outputs are tied altogether to perform an OR function and are connected to said output terminal (33) to have a multi emitter like circuit. The pull down block (32) in this embodiment is comprised of 2 FETs (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z) the gate of which is connected to said output node OUT. These 2 FETs are for driving a NPN pull down transistor (T), the collector of which is also connected to the output node OUT.
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Biagio J Pluchino from Lagrangeville, NY, age ~68 Get Report