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Barry A Giffel

from Wake Forest, NC
Age ~56
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Also known as:
Barry Andrew Giffel, Arry A Giffel
Related to:
Janetta D Jones, 54Kerri Lynn Williams, 46Cody J Collins, 43Michael E Duty, 47John CollinsMelissa Hibben, 42Tammy Frakes, 46
Connected to:
Adrianne Giffen, 43Allison E Giffen, 41Elisa A Giffen, 59Kevin G Giffen, 72Lisa M Giffen, 46Maria E Giffen, 45Matthew S Giffen, 40Stephen C Giffen, 55Thomas C Giffen, 55Courtney L Giffey, 37

Barry Giffel Phones & Addresses

  • Wake Forest, NC
  • 12501 Village Meadows Ct, Raleigh, NC 27614
  • 1820 Avent Ridge Rd, Raleigh, NC 27606 (919) 859-1207
  • 1635 Pond Glen Way, Cary, NC 27513
  • Port Charlotte, FL
  • Charlotte, NC
  • Wade, NC

Work

Company: Synopsys Aug 1993 to Mar 2020 Position: Staff engineer

Education

School / High School: University of North Carolina at Charlotte

Industries

Computer Software

Resumes

Resumes

Barry Giffel Photo 1

Software Engineer

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Location:
6828 Barham Hollow Dr, Wake Forest, NC 27587
Industry:
Computer Software
Work:
Synopsys Aug 1993 - Mar 2020
Staff Engineer
Triad Semiconductor Aug 1993 - Mar 2020
Software Engineer
Education:
University of North Carolina at Charlotte

Publications

Us Patents

Routing Variants In Electronic Design Automation

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US Patent:
8245175, Aug 14, 2012
Filed:
Oct 23, 2009
Appl. No.:
12/605046
Inventors:
Barry A. Giffel - Wake Forest NC, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716126, 716129, 716130
Abstract:
Some embodiments provide a system that facilitates the creation of a schematic in an electronic design automation (EDA) application. During operation, the system obtains a source point and a destination point in the schematic from a user of the EDA application. Next, the system uses a line-probe-search technique to generate a set of route variants between the source point and the destination point. The system then provides the route variants to the user through a graphical user interface (GUI) in the EDA application and obtains, from the user, a selection of a route variant from the route variants through the GUI. Finally, the system uses the selected route variant as a route in the schematic.

Connection Navigation In Electronic Design Automation

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US Patent:
8438530, May 7, 2013
Filed:
Oct 30, 2009
Appl. No.:
12/609944
Inventors:
Barry A. Giffel - Wake Forest NC, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 15/04
G06F 17/50
US Classification:
716139
Abstract:
Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system obtains a set of parameters associated with parameterized connections in a hierarchy of the design and a set of net assignments to the parameters. Next, the system displays the parameters and the net assignments to a user of the EDA application through a graphical user interface (GUI) associated with the EDA application. Finally, the system enables modifications to the net assignments by the user through the GUI.

Dynamic Rule Checking In Electronic Design Automation

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US Patent:
20110023001, Jan 27, 2011
Filed:
Oct 14, 2009
Appl. No.:
12/579309
Inventors:
Barry A. Giffel - Wake Forest NC, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716122, 716139
Abstract:
Some embodiments provide a system that provides design rule checking in an electronic design automation (EDA) application. During operation, the system detects a change to a schematic by a user of the EDA application. Next, the system automatically applies a set of dynamic design rules to the schematic upon detecting the change. Finally, the system notifies the user of a rule violation if the schematic violates one or more of the dynamic design rules. The system allows the user to specify which dynamic rules to apply when the user is modifying the schematic.

Loop Removal In Electronic Design Automation

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US Patent:
20110025705, Feb 3, 2011
Filed:
Oct 20, 2009
Appl. No.:
12/582264
Inventors:
Barry A. Giffel - Wake Forest NC, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G09G 5/00
G06F 3/048
US Classification:
345619, 715764
Abstract:
Some embodiments provide a system that facilitates graphical object creation in an electronic design automation (EDA) application. During operation, the system uses a cursor to obtain a sequence of points from a user for creating a graphical object in a layout. Next, the system detects a loop in the graphical object based at least on the sequence of points and a current position of the cursor. Finally, the system modifies the sequence of points to remove the loop from the graphical object.

Technique For Generating An Analysis Equation

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US Patent:
20110107252, May 5, 2011
Filed:
Oct 30, 2009
Appl. No.:
12/609572
Inventors:
Anil P. Balaram - Nepean, CA
Kristin M. Beggs - Oviedo FL, US
Barry A. Giffel - Wake Forest NC, US
Guy M. Morency - Chapel Hill NC, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G06F 3/048
G06F 17/50
US Classification:
715773, 715803, 715862, 715771, 715810, 715843, 716139
Abstract:
During a method, a hybrid graphical user interface (GUI), which is associated with electronic-design-automation (EDA) software, is displayed. This hybrid GUI allows users to efficiently specify useful analysis equations using textual and/or graphical information. In particular, the hybrid GUI has a first window that includes graphical objects associated with a circuit design. A user can select one or more of the graphical objects and associated electrical parameters using a user-interface device, such as a mouse. The hybrid GUI has a second window that has icons and other graphical controls that allow the construction of an analysis equation using the user-interface device. In addition, the hybrid GUI has a third window that includes an equation editor that provides a symbolic representation of an analysis equation based at least on one or more text entries provided by a user using a second user-interface device (such as a keyboard) and/or user selections of a given graphical object in the graphical objects and an associated electrical parameter.

Integrated Circuit Design Using Generation And Instantiation Of Circuit Stencils

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US Patent:
20180089340, Mar 29, 2018
Filed:
Nov 10, 2017
Appl. No.:
15/809869
Inventors:
- Mountain View CA, US
Donald John Oriordan - Sunnyvale CA, US
Jonathan Lee Sanders - Santa Clara CA, US
Salem Lee Ganzhorn - Apex NC, US
Barry Andrew Giffel - Wake Forest NC, US
International Classification:
G06F 17/50
Abstract:
Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.

Integrated Circuit Design Using Generation And Instantiation Of Circuit Stencils

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US Patent:
20170249416, Aug 31, 2017
Filed:
Feb 24, 2017
Appl. No.:
15/442338
Inventors:
- Mountain View CA, US
Donald John Oriordan - Sunnyvale CA, US
Jonathan Lee Sanders - Santa Clara CA, US
Salem Lee Ganzhorn - Apex NC, US
Barry Andrew Giffel - Wake Forest NC, US
International Classification:
G06F 17/50
Abstract:
Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.
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Barry A Giffel from Wake Forest, NC, age ~56 Get Report