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Balaji K Vijayan

from Tahoe City, CA
Age ~37
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Also known as:
Balaji Kumaran Vijayan, Balaji K Vijanyan
Connected to:
Arjun Vijayanarayanan, 37Rajani V Vijayan, 45Shyni Vijayan, 40Sowrabha N Vijayanna, 44Tony Vijayan, 58Vidya Vijayan, 47Vijish Vijayan, 53Vinish Vijayan, 42Vinoy Vijayan, 41Archana Vijayaraghavan, 41

Balaji Vijayan Phones & Addresses

  • Tahoe City, CA
  • San Francisco, CA
  • 2811 Rio Grande St APT 302, Austin, TX 78705
  • 806 W 24Th St #318, Austin, TX 78705
  • Houston, TX
  • Sugar Land, TX
  • Burlington, MA

Work

Company: Quotient solutions, inc. Feb 2013 Address: Austin Position: Project manager

Education

Degree: BBA School / High School: The University of Texas at Austin - The Red McCombs School of Business 2005 to 2008 Specialities: Supply Chain Management, MIS

Skills

Business Analysis • Product Management • IT Strategy • Business Strategy • Software Development • Consulting • Software Development Life Cycle • Process Improvement • Training • Testing • Information Technology • Business Process Improvement • Requirements Gathering • Requirements Analysis • Business Process • Cross-functional Team Leadership • Software Project Management • Visio • SharePoint • Agile Methodologies • SDLC • Data Analysis • Management Consulting • Agile Project Management • Change Management

Languages

English • German • Tamil

Industries

Information Technology and Services

Resumes

Resumes

Balaji Vijayan Photo 1

Software Technology Consultant

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Position:
Project Manager at Quotient Solutions, Inc.
Location:
Austin, Texas
Industry:
Information Technology and Services
Work:
Quotient Solutions, Inc. - Austin since Feb 2013
Project Manager
Seilevel - Austin, Texas Area Nov 2010 - Feb 2013
Product Manager
Quorum Business Solutions - Houston, Texas Area Feb 2009 - Oct 2010
Consultant
BearingPoint - Austin, Texas Area May 2008 - Jan 2009
Intern - Public Services
Friends of Alec - Austin, Texas Area Sep 2005 - Dec 2008
Student Manager
Education:
The University of Texas at Austin - The Red McCombs School of Business 2005 - 2008
BBA, Supply Chain Management, MIS The University of Texas at Austin 2005 - 2008
B.A., Government
Skills:
Business Analysis
Product Management
IT Strategy
Business Strategy
Software Development
Consulting
Software Development Life Cycle
Process Improvement
Training
Testing
Information Technology
Business Process Improvement
Requirements Gathering
Requirements Analysis
Business Process
Cross-functional Team Leadership
Software Project Management
Visio
SharePoint
Agile Methodologies
SDLC
Data Analysis
Management Consulting
Agile Project Management
Change Management
Languages:
English
German
Tamil

Publications

Us Patents

Merging Memory Ordering Tracking Information For Issued Load Instructions

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US Patent:
20210026632, Jan 28, 2021
Filed:
Jul 25, 2019
Appl. No.:
16/521663
Inventors:
- Cambridge, GB
Balaji VIJAYAN - Austin TX, US
Huzefa Moiz SANJELIWALA - Austin TX, US
Sharmila SHRIDHAR - Austin TX, US
International Classification:
G06F 9/30
Abstract:
An apparatus is described, comprising load issuing circuitry configured to issue load operations to load data from memory, and memory ordering tracking storage circuitry configured to store memory ordering tracking information on issued load operations. The apparatus also includes control circuitry configured to access the memory ordering tracking storage circuitry to determine, using the memory ordering tracking information, whether at least one load operation has been issued in disagreement with a memory ordering requirement, and, if so, to determine whether to re-issue one or more issued load operations or to continue issuing load operations despite disagreement with the memory ordering requirement. Furthermore, the control circuitry is capable of merging the memory ordering tracking information for a plurality of issued load operations into a merged entry in the memory ordering tracking storage circuitry.

Prefetching Techniques

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US Patent:
20200097409, Mar 26, 2020
Filed:
Sep 24, 2018
Appl. No.:
16/139160
Inventors:
- Cambridge, GB
Chris Abernathy - Austin TX, US
Huzefa Moiz Sanjeliwala - Austin TX, US
Dam Sunwoo - Austin TX, US
Balaji Vijayan - Austin TX, US
International Classification:
G06F 12/0862
G06F 9/30
Abstract:
A variety of data processing apparatuses are provided in which stride determination circuitry determines a stride value as a difference between a current address and a previously received address. Stride storage circuitry stores an association between stride values determined by the stride determination circuitry and a frequency during a training period. Prefetch circuitry causes a further data value to be proactively retrieved from a further address. The further address is the current address modified by a stride value in the stride storage circuitry having a highest frequency during the training period. The variety of data processing apparatuses are directed towards improving efficiency by variously disregarding certain candidate stride values, considering additional further addresses for prefetching by using multiple stride values, using feedback to adjust the training process and compensating for page table boundaries.

Instruction Boundary Prediction For Variable Length Instruction Set

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US Patent:
20140281246, Sep 18, 2014
Filed:
Mar 15, 2013
Appl. No.:
13/836374
Inventors:
Mauricio Breternitz, JR. - Austin TX, US
Youfeng Wu - Palo Alto CA, US
Peter Sassone - Austin TX, US
James Mason - Austin TX, US
Aashish Phansalkar - Austin TX, US
Balaji Vijayan - Austin TX, US
International Classification:
G06F 12/08
US Classification:
711125
Abstract:
A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.
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Balaji K Vijayan from Tahoe City, CA, age ~37 Get Report