Inventors:
Allen Baisuck - San Jose CA
Richard L. Fairbank - Schenectady NY
Walter K. Gowen - Troy NY
Jon R. Henriksen - Latham NY
William W. Hoover - Ballston Lake NY
Judith A. Huckabay - Union City CA
Eric Rogoyski - Los Gatos CA
Anton G. Salecker - Clifton Park NY
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 1750
Abstract:
A system for model-based verification of local design rules comprises a processing unit, a verification database wherein a cell reference graph representing an integrated circuit design as a hierarchical collection of cells is stored, a verification function memory wherein a verification function is stored, a friendly worklayer memory, and an unfriendly worklayer memory. Each cell can include shape models and references to lower-level cells. The processing unit first verifies each cell in the cell reference graph that does not reference any lower-level cells, after which the processing unit verifies each cell for which all lower-level cells referenced have been previously verified. During the verification of a selected cell, the processing unit determines whether models in the selected cell interact with other models in the selected cell or with any lower-level cell. Interacting models are referred to as being "unfriendly," and non-interacting models are referred to as being "friendly.