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Anthony G Bessios

from Saint Petersburg, FL
Age ~58
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Related to:
Diane M Phillips, 72Grace Sapa Guarte, 46Maria Guarte, 56Jesus GuartePatricia Bessios, 55
Connected to:
Joel D Bessire, 46Terry L Bessire, 58Thierry C Bessis, 60Benjamin J Bessler, 41Candy L Bessler, 66Donald J Bessler, 65Joseph E Bessler, 67Laurie L Bessler, 57Marjorie J Bessler, 60Valerie H Bessler, 63

Anthony Bessios Phones & Addresses

  • Saint Petersburg, FL
  • Pittsburgh, PA
  • 209 Braun Dr, Canonsburg, PA 15317
  • 39469 Gallaudet Dr, Fremont, CA 94538 (510) 793-8131
  • Gallaudet Dr, Fremont, CA 94538
  • Allentown, PA
  • Lansdale, PA
  • Brighton, MA
  • Los Angeles, CA
  • Dallas, TX

Work

Position: Tampa and st petersburg, florida area

Skills

Semiconductors • Asic • Embedded Systems • Circuit Design • Algorithms • Simulations • Signal Processing • Ic • Verilog • Product Management • Digital Signal Processors • R&D • Eda • Fpga • Matlab • Soc • Mixed Signal • Vlsi • System Architecture • Electronics • Start Ups • C • Mathematical Modeling • Systems Engineering • Rtl Design • Power Systems • Classroom Management • E Learning • Educational Technology • Usability • Usability Testing • Business Strategy • Operations Management

Languages

English • Greek • French

Ranks

Certificate: Edx Verified Certificate For Circuits and Electronics 2: Amplification, Speed, and Delay

Industries

Higher Education

Resumes

Resumes

Anthony Bessios Photo 1

Tampa And St Petersburg, Florida Area

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Location:
Pittsburgh, PA
Industry:
Higher Education
Work:

Tampa and St Petersburg, Florida Area
Skills:
Semiconductors
Asic
Embedded Systems
Circuit Design
Algorithms
Simulations
Signal Processing
Ic
Verilog
Product Management
Digital Signal Processors
R&D
Eda
Fpga
Matlab
Soc
Mixed Signal
Vlsi
System Architecture
Electronics
Start Ups
C
Mathematical Modeling
Systems Engineering
Rtl Design
Power Systems
Classroom Management
E Learning
Educational Technology
Usability
Usability Testing
Business Strategy
Operations Management
Languages:
English
Greek
French
Certifications:
Edx Verified Certificate For Circuits and Electronics 2: Amplification, Speed, and Delay
Edx Honor Code Certificate For Control System Design – A First Look
Edx Verified Certificate For Electronic Materials and Devices
Edx Verified Certificate For Optical Materials and Devices
Edx Verified Certificate For Magnetic Materials and Devices
Edx
Linkedin

Publications

Us Patents

Parity-Check Coding For Efficient Processing Of Decoder Error Events In Data Storage, Communication And Other Systems

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US Patent:
6543023, Apr 1, 2003
Filed:
Feb 5, 2001
Appl. No.:
09/776653
Inventors:
Anthony Bessios - Fremont CA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03M 1300
US Classification:
714758, 714800
Abstract:
A sequence of information bits are parity-check coded in a parity generator utilizing an m+1-bit parity-check code. The m+1-bit parity-check code may be formed as a combination of an otherwise conventional m-bit parity-check code and an overall parity bit. The overall parity bit provides an indication of the parity of a plurality of composite or single error events associated with decoding of the parity codewords. The parity generator includes a single-parity encoder for generating the overall parity bit, and a parity generator matrix element for generating a codeword based on the m-bit parity-check code, with a given one of the codewords of the m+1-bit parity-check code formed as a combination of the codeword based on the m-bit parity-check code and the overall parity bit. The invention can be used with any conventional m-bit parity-check code to produce an m+1-bit enhanced parity-check code with K=N-m and rate where N+1 denotes the total number of bits in a given one of the m+1-bit parity codewords.

Product Code With Interleaving To Enhance Error Detection And Correction

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US Patent:
6606718, Aug 12, 2003
Filed:
May 11, 2000
Appl. No.:
09/569129
Inventors:
Anthony G. Bessios - Allentown PA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G06F 1100
US Classification:
714701, 714804
Abstract:
A product code and interleaving/de-interleaving process are designed to work in combination to improve the coding gain of the product code. Such improvement of coding gain is based on an error constraint. The error constraint is a maximum number of values in error per block in the detected decisions for received output channel samples. The error constraint may be a burst error constraint, such as a maximum number of errors in a block introduced by burst noise in the communication channel; or the error constraint may be an error event constraint, such as the error event generated by an incorrect decision for a path through the trellis of the Viterbi algorithm employed by the detector or a combination of both. In one implementation, a block of data of length N is encoded with a product code of two dimensions with N a positive integer. The product code includes an error correcting capability of detection and correction by a receiver of single one-bit errors in the encoded block.

Compensation For Polarization Mode Dispersion In Single Mode Fiber

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US Patent:
6862413, Mar 1, 2005
Filed:
Dec 21, 2001
Appl. No.:
10/036750
Inventors:
Anthony Bessios - Fremont CA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04B010/06
US Classification:
398208, 398205, 398147, 398159, 375317
Abstract:
A receiver employs non-linear threshold compensation to adjust input sample values from a single mode fiber to mitigate effects of polarization mode dispersion. A difference S between values for i) a decision for the current input sample and ii) a decision for the previous input sample is generated that indicates whether a transition between logic values occurred in the input data and the direction of transition (sign/phase). Two values are generated to determine a magnitude c of correction combined with the sign/phase (difference S) to generate a correction value. An error value e is generated as the magnitude of the difference between i) the decision for the input sample and ii) the input sample. A value d is calculated as the magnitude of the difference between i) the current input sample and ii) the previous input sample is also generated. The value d represents a relative “closeness” in value between two consecutive input samples.

Technique For Improving The Quality Of Digital Signals In A Multi-Level Signaling System

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US Patent:
6917312, Jul 12, 2005
Filed:
Nov 10, 2003
Appl. No.:
10/703631
Inventors:
Anthony Bessios - Fremont CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03M005/02
US Classification:
341 56, 341 58, 341 59, 375286, 375353
Abstract:
A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method may comprise encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is formed to reduce full-swing transitions between successive digital signal transmissions.

High Speed Signaling System With Adaptive Transmit Pre-Emphasis And Reflection Cancellation

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US Patent:
7030657, Apr 18, 2006
Filed:
May 21, 2004
Appl. No.:
10/851505
Inventors:
Vladimir M. Stojanovic - Stanford CA, US
Andrew Ho - Palo Alto CA, US
Anthony Bessios - Fremont CA, US
Fred F. Chen - San Francisco CA, US
Elad Alon - Saratoga CA, US
Mark A. Horowitz - Menlo Park CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03K 19/0175
US Classification:
326 87, 326 83
Abstract:
A signaling system having an equalizing transmitter and equalizing receiver. The equalizing transmitter transmits a signal to a receive circuit. A first sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a first threshold, and a second sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a second threshold. A drive strength of the equalizing transmitter and a drive strength of an equalizing signal driver within the equalizer are adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds.

Compensation Of Polarization Mode Dispersion In Single Mode Fiber For Maximum-Likelihood Sequence Estimation

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US Patent:
7110683, Sep 19, 2006
Filed:
Dec 26, 2001
Appl. No.:
10/035928
Inventors:
Anthony Bessios - Fremont CA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04B 10/06
US Classification:
398208, 398149, 398159
Abstract:
An output signal of a single mode fiber (SMF) is spectrally shaped to achieve characteristics of a predefined channel “target” response. The target response is that of a partial-response, maximum-likelihood channel with additive white Gaussian noise. A receiver employs a maximum-likelihood sequence estimation (MLSE) detector having its detection algorithm, such as a Viterbi algorithm (VA), matched to the target response. Thus, state, branch, and path metric calculations for a Viterbi trellis may be optimized for a channel having this target response.

Technique For Improving The Quality Of Digital Signals In A Multi-Level Signaling System

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US Patent:
7113550, Sep 26, 2006
Filed:
Dec 10, 2002
Appl. No.:
10/314985
Inventors:
William Stonecypher - San Jose CA, US
Anthony Bessios - Fremont CA, US
Amita Agarwal - Baltimore MD, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H04L 25/34
US Classification:
375288, 375353, 341 56
Abstract:
A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method comprises encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is selected to eliminate full-swing transitions between successive digital signal transmissions. The method also comprises transmitting the sets of P symbols.

High Speed Signaling System With Adaptive Transmit Pre-Emphasis

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US Patent:
7126378, Oct 24, 2006
Filed:
Dec 17, 2003
Appl. No.:
10/740087
Inventors:
Vladimir M. Stojanovic - Stanford CA, US
Andrew C. C. Ho - Palo Alto CA, US
Anthony Bessios - Fremont CA, US
Fred F. Chen - San Francisco CA, US
Elad Alon - Saratoga CA, US
Mark A. Horowitz - Menlo Park CA, US
Assignee:
Rambus, Inc. - Los Altos CA
International Classification:
H03K 19/0175
US Classification:
326 87, 326 83, 326 27
Abstract:
A signaling system having first and second sampling circuits and an output driver circuit. The first sampling circuit samples a first signal generated by the output driver circuit to determine whether the first signal exceeds a first threshold. The second sampling circuit samples the first signal to determine whether the first signal exceeds a second threshold. The drive strength of the output driver circuit is adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds, and the second threshold is adjusted based, at least in part, on whether the first signal exceeds the second threshold.
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Anthony G Bessios from Saint Petersburg, FL, age ~58 Get Report