Andrzej Jozef Strojwas

7906254, Mar 15, 2011

Oct 2, 2007

11/906736

Lawrence T. Pileggi - Pittsburgh PA, US
Andrzej J. Strojwas - Pittsburgh PA, US
Lucio L. Lanza - Palo Alto CA, US

PDF Solutions, Inc. - San Jose CA

G06F 17/50
G06F 19/00
G03F 1/00

430 5, 716 50, 716100, 700121

The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

20060112355, May 25, 2006

Nov 4, 2005

11/267569

Lawrence Pileggi - Pittsburgh PA, US
Andrzej Strojwas - Pittsburgh PA, US
Lucio Lanza - Palo Alto CA, US

Fabbrix, Inc. - Palo Alto CA

G06F 17/50

716001000, 716019000

The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

20060253810, Nov 9, 2006

Sep 16, 2003

10/572151

Carlo Guardiani - Verona, IT
Nicola Dragone - Vobarno, IT
John Kibarian - Los Altos CA, US
Enrico Malavasi - Mountain View CA, US
Rijko Radocic - San Diego CA, US
Andrzej Strojwas - Pittsburgh PA, US

G06F 17/50

716004000

Library design elements () are analyzed for manufacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process. The library design elements from a library are obtained. Manufacturability attributes () of the library design elements are determined for the particular manufacturing process, where manufacturability attributes include yield-related attributes. Library views () with manufacturability attributes for the library design elements are then generated, which are utilizing by an electronic design automation (EDA) tool.

20100162193, Jun 24, 2010

Jan 29, 2010

12/697161

Lawrence T. Pileggi - Pittsburgh PA, US
Andrzej J. Strojwas - Pittsburgh PA, US
Lucio L. Lanza - Palo Alto CA, US

G06F 17/50

716 10, 716 17

The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

20170178981, Jun 22, 2017

Apr 4, 2016

15/090256

- San Jose CA, US
Dennis Ciplickas - San Jose CA, US
Tomasz Brozek - Morgan Hill CA, US
Jeremy Cheng - San Jose CA, US
Simone Comensoli - Darfo Boario Terme, IT
Indranil De - Mountain View CA, US
Kelvin Doong - Hsinchu City, TW
Hans Eisenmann - Tutzing, DE
Timothy Fiscus - New Galilee PA, US
Jonathan Haigh - Pittsburgh PA, US
Christopher Hess - Belmont CA, US
John Kibarian - Los Altos Hills CA, US
Sherry Lee - Monte Sereno CA, US
Marci Liao - Santa Clara CA, US
Sheng-Che Lin - Hsinchu City, TW
Hideki Matsuhashi - Santa Clara CA, US
Kimon Michaels - Monte Sereno CA, US
Conor O'Sullivan - Campbell CA, US
Markus Rauscher - Munich, DE
Vyacheslav Rovner - Pittsburgh PA, US
Andrzej Strojwas - Pittsburgh PA, US
Marcin Strojwas - Pittsburgh PA, US
Carl Taylor - Pittsburgh PA, US
Rakesh Vallishayee - Dublin CA, US
Larg Weiland - Hollister CA, US
Nobuharu Yokoyama - Tokyo, JP

H01L 21/66

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

20150270181, Sep 24, 2015

Feb 3, 2015

14/612841

- San Jose CA, US
Dennis J. Ciplickas - San Jose CA, US
Stephen Lam - Freemont CA, US
Jonathan Haigh - Pittsburgh PA, US
Vyacheslav V. Rovner - Pittsburgh PA, US
Christopher Hess - Belmont CA, US
Tomasz W. Brozek - Morgan Hill CA, US
Andrzej J. Strojwas - Pittsburgh PA, US
Kelvin Doong - Zhubei City, TW
John K. Kibarian - Los Altos CA, US
Sherry F. Lee - Monte Sereno CA, US
Kimon W. Michaels - Monte Sereno CA, US
Marcin A. Strojwas - Pittsburgh PA, US
Conor O'Sullivan - Campbell CA, US
Mehul Jain - San Jose CA, US

H01L 21/66
G01R 31/26

Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.