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Anatoliy V Tsyrganovich

from Woodside, CA
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Also known as:
A Tsyrganovich, V Y
Phone and address:
500 Kebet Rdg, Redwood City, CA 94062
(408) 750-7930
Related to:
Svetlana G Tsyrganovich, 71G A
Connected to:
Slavic Tsytsyn, 46Stanislav Tsyupa, 40Yelena Tsyupa, 63Roman E Tsyvine, 68Victoria W Tsze, 35Gary R Tsztoo, 64Francine D Ttee, 99Bo Q Tu, 86Carolyn A Tu, 55Cau Tu, 82

Anatoliy Tsyrganovich Phones & Addresses

  • 500 Kebet Rdg, Redwood City, CA 94062 (408) 750-7930
  • Woodside, CA
  • 906 Windsor Hills Cir, San Jose, CA 95123 (408) 229-8825
  • Cupertino, CA
  • 906 Windsor Hills Cir, San Jose, CA 95123

Work

Company: Chargepoint, inc. Mar 2019 Position: Senior staff power engineer

Education

Degree: Doctorates, Doctor of Philosophy Specialities: Communications, Electronics

Skills

Embedded Systems • Mixed Signal • Semiconductors • Soc • Analog • Ic • Analog Circuit Design • Asic • Debugging • Microprocessors • Circuit Design • Rtl Coding • Verilog • Firmware • Power Management • Electronics • Integrated Circuit Design • Signal Processing • Mechanical Engineering • Team Building • Cross Functional Team Leadership • Audio Enhancement

Languages

English

Emails

a***[email protected]

Industries

Semiconductors

Resumes

Resumes

Anatoliy Tsyrganovich Photo 1

Senior Staff Power Engineer

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Location:
8972 Knoble Ct, Eden Prairie, MN 55347
Industry:
Semiconductors
Work:
Chargepoint, Inc.
Senior Staff Power Engineer
Ixys Corporation Jan 2013 - Dec 2018
Fellow, Systems Architect [email protected]
Stmicroelectronics Dec 2007 - Nov 2012
Principal Engineer
Teamplet May 2007 - Dec 2007
Co-Founder, Chief Technology Officer
Zilog May 1995 - Apr 2007
Fellow, Systems Engineering
Skills:
Embedded Systems
Mixed Signal
Semiconductors
Soc
Analog
Ic
Analog Circuit Design
Asic
Debugging
Microprocessors
Circuit Design
Rtl Coding
Verilog
Firmware
Power Management
Electronics
Integrated Circuit Design
Signal Processing
Mechanical Engineering
Team Building
Cross Functional Team Leadership
Audio Enhancement
Languages:
English

Publications

Us Patents

Method And Apparatus For Improved Signal Filtering

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US Patent:
6424384, Jul 23, 2002
Filed:
Jul 22, 1999
Appl. No.:
09/359259
Inventors:
Anatoliy V. Tsyrganovich - San Jose CA
Assignee:
Zilog, Inc. - Campbell CA
International Classification:
H04N 978
US Classification:
348666, 348665
Abstract:
A method and apparatus for separating a signal uses a low pass filtering in a first direction to produce a signal with a low component and a alias component and then uses a filtering in a second direction to produce a component of a separated signal. The filter has applications in television signal decoding and has other applications.

Circuit And Method That Allows The Amplitudes Of Vertical Correction Signal Components To Be Adjusted Independently

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US Patent:
6522091, Feb 18, 2003
Filed:
Oct 17, 2001
Appl. No.:
09/981579
Inventors:
Anatoliy V. Tsyrganovich - San Jose CA
Assignee:
ZiLOG, Inc. - San Jose CA
International Classification:
G09G 104
US Classification:
315371, 315370
Abstract:
The present disclosure describes a technique that allows the amplitudes of vertical correction signal components to be adjusted independently. When the amplitude of each of the vertical correction signal components are set, they will not have to be readjusted when the amplitudes of the other vertical correction signal components are set. This greatly simplifies the process of setting the amplitudes of the vertical correction signal components, saving time and increasing the accuracy of the settings.

Method And Apparatus For Improved Signal Restoration

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US Patent:
6529248, Mar 4, 2003
Filed:
Mar 29, 2000
Appl. No.:
09/538078
Inventors:
Anatoliy V. Tsyrganovich - San Jose CA
Assignee:
ZiLOG, Inc. - San Jose CA
International Classification:
H04N 506
US Classification:
348691, 348526, 348695, 348696, 348697, 348525, 348521
Abstract:
A method and/or apparatus is capable of performing high accuracy digital level restoration with a high degree of noise immunity provided by a passive clamping stage.

Analog Frequency Locked Loop With Digital Oversampling Feedback Control And Filter

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US Patent:
6636122, Oct 21, 2003
Filed:
Oct 9, 2001
Appl. No.:
09/973979
Inventors:
Anatoliy V. Tsyrganovich - San Jose CA
Assignee:
Zilog, Inc. - San Jose CA
International Classification:
H03L 700
US Classification:
331 25, 331 1 A, 331 16, 327160, 341143, 341142
Abstract:
A filter using analog to digital conversion, digital filtering and oversampling noise reshaping is disclosed. Application of such a filter to a frequency locked oscillator is disclosed. Application of such a filter to an oscillator having a capability to synchronize with an external stimulus is disclosed.

Scan Velocity Modulation Technique

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US Patent:
6674253, Jan 6, 2004
Filed:
Jan 3, 2002
Appl. No.:
10/038091
Inventors:
Anatoliy V. Tsyrganovich - San Jose CA
Assignee:
Zilog, Inc. - Campbell CA
International Classification:
G09G 104
US Classification:
315371, 315403, 315399, 315370, 315383, 348626, 348629
Abstract:
A video signal is split into a first signal and a second signal. The first signal includes low amplitude/high frequency components of the video signal, which can be properly amplified by a video amplifier. The second signal includes high amplitude/high frequency components of the video signal, which cannot be properly amplified by the video amplifier. The first signal is combined with the video signal, amplified by the video amplifier, and used to modulate the intensity of an electron beam. The second signal is amplified by a scan velocity modulation amplifier and used to modulate the horizontal scan velocity of the electron beam.

Circuit And Method For Reducing East-West Geometry Mismatch Between The Top And Bottom Of A Raster Display

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US Patent:
6717377, Apr 6, 2004
Filed:
Oct 31, 2001
Appl. No.:
10/003824
Inventors:
Anatoliy V. Tsyrganovich - San Jose CA
Assignee:
ZiLOG, Inc. - San Jose CA
International Classification:
H01J 2956
US Classification:
315371, 315364
Abstract:
The present disclosure describes a technique for reducing east-west geometry mismatch between the top and bottom of a raster display. This is accomplished by generating a horizontal correction signal that does not have any discontinuities. Since there are no discontinuities in the horizontal correction signal, the horizontal deflection current signal will not be distorted. As a result, there will be no east-west geometry mismatch between the top and bottom of the raster display.

Sigma-Delta Analog-To-Digital Converter With Reduced Quantization Noise

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US Patent:
6839010, Jan 4, 2005
Filed:
Dec 27, 2002
Appl. No.:
10/331037
Inventors:
Anatoliy V. Tsyrganovich - San Jose CA, US
Assignee:
ZiLOG, Inc. - San Jose CA
International Classification:
H03M 300
US Classification:
341143, 341144, 341155, 341172
Abstract:
An improved sigma-delta converter includes a post converter filter that receives a digital data stream. The data stream has a digital amplitude and contains quantization noise. Quantization noise is larger for digital amplitudes in a second larger-amplitude range than in a first smaller-amplitude range. The post converter filter has a higher cut-off frequency when the digital amplitude is in the first amplitude range and a lower cut-off frequency when the digital amplitude is in the second amplitude range. The post converter filter therefore filters out a portion of the larger quantization noise when the digital amplitude is larger. Quanitization noise is reduced without limiting the input signal voltage range that can be digitized.

Self-Calibrating Sigma-Delta Analog-To-Digital Converter

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US Patent:
6907374, Jun 14, 2005
Filed:
Mar 19, 2003
Appl. No.:
10/394114
Inventors:
Anatoliy V. Tsyrganovich - San Jose CA, US
Assignee:
ZiLOG, Inc. - San Jose CA
International Classification:
G01R035/00
US Classification:
702107, 702 79, 702124, 708307
Abstract:
A self-calibrating sigma-delta converter (SCADC) functions in a calibration mode and in an operational mode. In the calibration mode, a test circuit of the SCADC generates test signals that are periodic rectangular voltage waveforms. Each test signal has a dc component with a precise voltage amplitude, as well as harmonic components. A low-pass filter of a sigma-delta converter (SDC) within the SCADC filters out the harmonic components. A digital calibration processing circuit within the SCADC uses the precise voltage amplitudes to generate digital correction factors that compensate for dc offset error, gain error and INL error of the SDC. In the operational mode, the SDC receives an analog operational signal and outputs an operational digital data stream. The digital calibration processing circuit uses the correction factors to compensate for dc offset error, gain error and INL error in the operational digital data stream and outputs a corrected digital data stream.
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Anatoliy V Tsyrganovich from Woodside, CA Get Report