Search

Anatoli A Bolotov

from San Jose, CA
Age ~70
Get Report
Also known as:
Anatoli A Botolo, Anatolia Bolotov, Anatoli Boloton, Anatoli V
Related to:
Alexander A Bolotov, 36Daniel P Romero, 36Elena Bolotova, 65
Connected to:
Alexey V Bolotov, 37Viktor M Bolotov, 68Victor BolotskoCheryl A Bolotte, 61Gwen L Bolotte, 69Patricia P Bolou, 81Akbar Bolourchi, 96Elishia Bolour, 42Patrics Bolouvi, 49

Anatoli Bolotov Phones & Addresses

  • San Jose, CA
  • 7375 Rollingdell Ct, Cupertino, CA 95014 (408) 873-8132

Resumes

Resumes

Anatoli Bolotov Photo 1

Member Of The Board Of Trustees

View page
Location:
San Jose, CA
Industry:
Computer & Network Security
Work:
Lincoln University (Oakland, Ca)
Member of the Board of Trustees
Avago Technologies Apr 2014 - Nov 2014
Director and Distinguished Engineer
Lsi Corporation 2009 - 2014
Distinguished Engineer
Intel Corporation 2009 - 2014
Engineering Manager and Intel Principal Engineer
Education:
Moscow State Lomonosov University
Doctorates, Doctor of Philosophy, Mathematics
Skills:
Алгоритмы
Оптимизация
Установление Деловых Контактов
Полупроводниковые Технологии
Встраиваемые Системы
Asic
Отладка
Однокристальные Системы
Интегральные Схемы
C
Anatoli Bolotov Photo 2

Anatoli Bolotov

View page

Publications

Us Patents

Process For Solving Assignment Problems In Integrated Circuit Designs With Unimodal Object Penalty Functions And Linearly Ordered Set Of Boxes

View page
US Patent:
6453453, Sep 17, 2002
Filed:
Apr 11, 2001
Appl. No.:
09/833142
Inventors:
Alexander E. Andreev - San Jose CA
Anatoli A. Bolotov - Cupertino CA
Pedja Raspopovic - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 945
US Classification:
716 10, 716 2
Abstract:
A linear assignment problem for an ordered system containing a plurality of boxes each containing an object having an associated penalty function is solved. A hierarchy contains a bottom level containing at least as many generalized boxes as there are boxes in the assignment problem, and top and intermediate levels. The objects of the assignment problem are placed in the generalized box of the top level. A first local task is executed to transition the contents of a generalized box of a higher level to at least two generalized boxes of the next lower level. A second local task is executed on the generalized boxes of the lower level to minimize a global penalty function. The first and second tasks are executed through successive iterations until all of the objects are placed in the generalized boxes in the bottom level in a layout having minimal penalty function.

Channel Router With Buffer Insertion

View page
US Patent:
6505336, Jan 7, 2003
Filed:
Mar 13, 2001
Appl. No.:
09/804939
Inventors:
Alexander E. Andreev - San Jose CA
Pedja Raspopovic - Cupertino CA
Anatoli A. Bolotov - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1750
US Classification:
716 14, 716 12
Abstract:
Channels are routed in an integrated circuit layout by reserving grid positions for buffers. Cell pins are identified at different y-coordinates to be connected by the channel. A determination is made as to the necessity of a jog between vertical segments, and if so, a y-coordinate is assigned to each such jog. An x-coordinate is assigned to each channel segment extending across the y-coordinates. Y-coordinates are assigned to buffers to be connected to the channel.

Net Delay Optimization With Ramptime Violation Removal

View page
US Patent:
6507939, Jan 14, 2003
Filed:
May 15, 2001
Appl. No.:
09/858166
Inventors:
Alexander E. Andreev - San Jose CA
Anatoli A. Bolotov - Cupertino CA
Igor A. Vikhliantsev - Santa Clara CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1750
US Classification:
716 10, 716 2, 716 6
Abstract:
The specification discloses a for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves. The steps of the method include inserting a plurality of auxiliary nodes into the, defining discrete, approximate scales for delay, load, and ramp time, constructing a set of buffers chains for later insertion into the net tree, determining for each node on the tree a tradeoff function relating ramp time, departure time and load at the node, for each node, removing combinations of the tradeoff functions and the buffer chains, which when inserted into the tradeoff function, lead to a ramp time which exceeds a predetermined maximum allowable ramp time, for each node, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.

Fast Free Memory Address Controller

View page
US Patent:
6662287, Dec 9, 2003
Filed:
Oct 18, 2001
Appl. No.:
10/000243
Inventors:
Alexander E. Andreev - San Jose CA
Anatoli A. Bolotov - Cupertino CA
Ranko Scepanovic - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1200
US Classification:
711170, 711154, 711217, 707205
Abstract:
A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.

Memory That Allows Simultaneous Read Requests

View page
US Patent:
6886088, Apr 26, 2005
Filed:
Dec 3, 2002
Appl. No.:
10/308334
Inventors:
Egor A. Andreev - San Jose CA, US
Anatoli A. Bolotov - Cupertino CA, US
Ranko Scepanovic - San Jose CA, US
Alexander E. Andreev - San Jose CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F013/00
US Classification:
711168, 711 5, 711104, 711173, 711220
Abstract:
The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.

Process For Designing Comparators And Adders Of Small Depth

View page
US Patent:
7020865, Mar 28, 2006
Filed:
Jun 24, 2003
Appl. No.:
10/602570
Inventors:
Mikhail I. Grinchuk - San Jose CA, US
Anatoli A. Bolotov - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 18, 716 2, 716 3, 716 7
Abstract:
Logic circuits for logical operations, based on a function f=xOR (xAND (xOR (xAND. . . x. . . ))) or f′=xAND (xOR (xAND (xOR. . . x. . . ))), are designed by defining a top portion of the logic circuit based on a pre-selected pattern of 2-input $ and @ gates. The top portion has N inputs and approximately N/3 outputs. A smaller logic circuit is defined having approximately N/3 inputs coupled to the outputs of the top portion. In one embodiment, the circuit is designed for a circuit having N′ inputs, where N′ is 3or 2*3, and the N′−N most significant inputs are set to fixed values. The extra gates are removed resulting in a minimum depth circuit. In another embodiment, the depth is further reduced in some cases by designing a circuit for N−1 inputs and transforming the circuit to an N-input circuit. The $ and @ gates are converted to AND and/or OR gates, depending on the function.

Method For Generating Tech-Library For Logic Function

View page
US Patent:
7062726, Jun 13, 2006
Filed:
Apr 30, 2003
Appl. No.:
10/426549
Inventors:
Alexander E. Andreev - San Jose CA, US
Igor A. Vikhliantsev - Sunnyvale CA, US
Anatoli A. Bolotov - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 3, 716 18
Abstract:
The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library. When the number of elements in the tech-library is at least twice larger than a limit, the number is reduced.

Integrated Circuit And Process For Identifying Minimum Or Maximum Input Value Among Plural Inputs

View page
US Patent:
7072922, Jul 4, 2006
Filed:
Dec 13, 2002
Appl. No.:
10/319219
Inventors:
Alexander E. Andreev - San Jose CA, US
Anatoli A. Bolotov - Cupertino CA, US
Igor Vikhliantsev - Sunnyvale CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 15/00
US Classification:
708207
Abstract:
Apparatus and process identifies a maximum or minimum value among a plurality of binary values on a plurality of a-bit wide wires in an integrated circuit module. An N-bit vector K is calculated based on n most significant bits of all a-bit binary signals, where N=2. M N-bit vectors K,. . . ,K_(M−1) are calculated based on the n most significant and the m least significant bits of all a-bit binary signals, where M is at least 2−1. A table is constructed from vectors K,. . . ,K(M−1) to create table vectors. A table vector is selected based on vector K, is used to derive a vector P, which in turn is used to select another table vector. The minimum or maximum binary value is identified from the two selected table vectors.
Control profile
Anatoli A Bolotov from San Jose, CA, age ~70 Get Report