Search

Alykhan Madhani Phones & Addresses

  • Bellevue, WA
  • Albuquerque, NM
  • Seatac, WA
  • Santa Clara, CA

Work

Company: Htc Jan 2010 to Aug 2013 Position: Quality account manager

Skills

Six Sigma • Consumer Electronics • Product Development • Testing • Manufacturing • Integration • Project Management • Product Management • Cross-functional Team Leadership • Semiconductors • IC • Quality Management • Failure Analysis • Product Engineering • FMEA • Root Cause Analysis • SPC • Design of Experiments • Mobile Devices

Awards

Patents awarded regarding SONOS memory c... • "The Effects of Double-Sided Scrubbing o...

Ranks

Certificate: Six Sigma Green Belt Organization: ASQ

Industries

Consumer Electronics

Resumes

Resumes

Alykhan Madhani Photo 1

Quality Account Manager At Htc

View page
Position:
Quality Account Manager at HTC
Location:
Greater Seattle Area
Industry:
Consumer Electronics
Work:
HTC since Jan 2010
Quality Account Manager

ARRIS Oct 2009 - Jan 2010
Manager, Software Engineering-Certifications and Hardware Validation

Digeo Jun 2007 - Oct 2009
Manager, Certifications and Hardware Validation

Digeo Jun 2007 - Jan 2008
Sr. Systems Integration Hardware Validation Engineer

ZiLOG, Inc. Dec 2004 - Apr 2007
Sr. Product Engineer
Skills:
Six Sigma
Consumer Electronics
Product Development
Testing
Manufacturing
Integration
Project Management
Product Management
Cross-functional Team Leadership
Semiconductors
IC
Quality Management
Failure Analysis
Product Engineering
FMEA
Root Cause Analysis
SPC
Design of Experiments
Mobile Devices
Honor & Awards:
•Patents awarded regarding SONOS memory cell read/write/erase functionalities including: #7,009,887, #6,967,873 , #6,778,442, #6,768,673 •"The Effects of Double-Sided Scrubbing on Removal of Particles and Metal Contamination From Chemical-Mechanical Polished Wafers," (co-author) D.L. Hetherington, M. Ravkin,, DUMIC 1995.
Certifications:
Six Sigma Green Belt, ASQ

Publications

Us Patents

Method Of Dual Cell Memory Device Operation For Improved End-Of-Life Read Margin

View page
US Patent:
6778442, Aug 17, 2004
Filed:
Apr 24, 2003
Appl. No.:
10/422092
Inventors:
Darlene G. Hamilton - San Jose CA
Edward Hsia - Saratoga CA
Kulachet Tanpairoj - Palo Alto CA
Alykhan Madhani - Santa Clara CA
Mimi Lee - Santa Clara CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1134
US Classification:
36518528, 36518522
Abstract:
A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage. According to another aspect of the method, the method can include programming the first and second charge storing cells to the same data state and verifying that the second programmed charge storing cell stores charge corresponding to the data state. If the verification fails, both charge storing cells can be re-pulsed.

Memory Device And Method Using Positive Gate Stress To Recover Overerased Cell

View page
US Patent:
6967873, Nov 22, 2005
Filed:
Oct 2, 2003
Appl. No.:
10/677790
Inventors:
Darlene G. Hamilton - San Jose CA,
Zhizheng Liu - Sunnyvale CA,
Mark W. Randolph - San Jose CA,
Yi He - Freemont CA,
Edward Hsia - Saratoga CA,
Kulachet Tanpairoj - Palo Alto CA,
Mimi Lee - Santa Clara CA,
Alykhan Madhani - Santa Clara CA,
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C011/34
US Classification:
3651853, 36518529
Abstract:
A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

Method Of Determining Voltage Compensation For Flash Memory Devices

View page
US Patent:
7009887, Mar 7, 2006
Filed:
Jun 3, 2004
Appl. No.:
10/860450
Inventors:
Ed Hsia - Saratoga CA,
Darlene Hamilton - San Jose CA,
Alykhan Madhani - Santa Clara CA,
Kenneth Yu - San Francisco CA,
Assignee:
FASL LLC - Sunnyvale CA
International Classification:
G11C 16/04
US Classification:
36518528, 36518503, 36518519, 36518524
Abstract:
The present invention determines or identifies programming variations for different groups within an array or memory device that properly program memory cells within the respective groups. Then, during programming operations for a given memory cell, programming voltages are applied according to the determined or identified programming variations for the group to which the given memory cell belongs. These adjusted programming variations facilitate successful programming of the particular memory cell.

Quad Bit Using Hot-Hole Erase For Cbd Control

View page
US Patent:
7113431, Sep 26, 2006
Filed:
Mar 29, 2005
Appl. No.:
11/091982
Inventors:
Darlene Hamilton - San Jose CA,
Alykhan Madhani - Santa Clara CA,
Fatima Bathul - Cupertino CA,
Satoshi Torii - Sunnyvale CA,
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
G11C 16/14
US Classification:
36518529, 36518503, 36518502
Abstract:
The present invention pertains to a technique for erasing bits in a dual bit memory in a manner that maintains complementary bit disturb control of bit-pairs of memory cells wherein each bit of the dual bit memory cell can be programmed to multiple levels. One exemplary method comprises providing a word of memory cells after an initial erasure and programming of the bits of the word to one or more of the higher program levels. A disturb level is determined for each of the bit-pairs of the word. A combined disturb level is then computed that is representative of the individual disturb levels. A pattern of drain voltages is then applied to the word for a number of program passes until a target pattern is stored in the word of memory cells based on the combined disturb level and the unprogrammed bit of the bit-pairs is erased to a single program level. In this manner the present invention compensates for the disturbance level that exists between the complementary bit-pairs of the word, improves the Vt distribution at the program level of the erased state and thereby improves the accuracy of subsequent higher level programming operations and mitigates false or erroneous reads of the states of such program levels.

Method Of Determining Voltage Compensation For Flash Memory Devices

View page
US Patent:
7440333, Oct 21, 2008
Filed:
Jan 27, 2006
Appl. No.:
11/340916
Inventors:
Ed Hsia - Saratoga CA,
Darlene Hamilton - San Jose CA,
Alykhan Madhani - Santa Clara CA,
Kenneth Yu - San Francisco CA,
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
G11C 16/04
G11C 16/06
US Classification:
36518528, 36518522
Abstract:
The present invention determines or identifies programming variations for different groups within an array or memory device that properly program memory cells within the respective groups. Then, during programming operations for a given memory cell, programming voltages are applied according to the determined or identified programming variations for the group to which the given memory cell belongs. These adjusted programming variations facilitate successful programming of the particular memory cell.

Method Of Programming And Reading A Dual Cell Memory Device

View page
US Patent:
6768673, Jul 27, 2004
Filed:
Apr 24, 2003
Appl. No.:
10/422276
Inventors:
Edward Hsia - Saratoga CA
Darlene Hamilton - San Jose CA
Kulachet Tanpairoj - Palo Alto CA
Mimi Lee - Santa Clara CA
Alykhan F. Madhani - Santa Clara CA
Yi He - Fremont CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518503, 36518524
Abstract:
A method of programming and reading a dual cell memory device. The method includes storing a selected program level in each cell and reading one of the cells to determine a single data value stored by the memory device.
Alykhan F Madhani from Bellevue, WA, age ~52 Get Report