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Allen W Hairston

from Andover, MA
Age ~64

Allen Hairston Phones & Addresses

  • 39 Rattlesnake Hill Rd, Andover, MA 01810 (978) 475-8749
  • Winchester, MA
  • Arlington, MA
  • Easton, MD
  • 39 Rattlesnake Hill Rd, Andover, MA 01810

Work

Position: Executive, Administrative, and Managerial Occupations

Publications

Us Patents

Automatic Integration Reset Offset Subtraction Circuit

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US Patent:
7026853, Apr 11, 2006
Filed:
Jun 15, 2004
Appl. No.:
10/868429
Inventors:
Allen W. Hairston - Andover MA, US
Assignee:
BAE Systems Information and Electronic Systems Integration INC - Nashua NH
International Classification:
H03L 5/00
US Classification:
327307
Abstract:
Techniques for precise removal of offset charge associated with the reset switch of an integration circuit are disclosed. Offset cancellation circuitry includes a single reset offset subtraction circuit and a replica integrator, which is configured identically to the integrators to be offset cancelled. An offset charge is generated by the circuitry and capacitively coupled to the target integrators. This generated offset charge causes voltage at the input node of each target integrator to substantially match the desired starting voltage level of the targeted integration process. Minimal additional space and circuitry is needed. All of the undesired offset charge is cancelled, without canceling any of the desired input current.

Sliding Cascode Circuit

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US Patent:
7151412, Dec 19, 2006
Filed:
Aug 30, 2004
Appl. No.:
10/929604
Inventors:
Allen W Hairston - Andover MA, US
Assignee:
Bae Systems Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H03F 3/16
US Classification:
330311, 330277, 330291
Abstract:
Described techniques extend (e. g. , by a factor of 2) the dynamic range of voltage swing for amplifiers and other integrated circuits (e. g. , buffers) that are fabricated using lower voltage rated semiconductor processes. Such processes include, for instance, thin gate oxide MOS, and other semiconductor processes that provide desirable features that are typically not associated with high voltage processes, such as increased radiation hardness, higher speed logic, and compactness. Thus, relatively large dynamic range is enabled for integrated circuits fabricated using feature-rich lower voltage rated semiconductor processes.

Substitution Of Defective Readout Circuits In Imagers

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US Patent:
7852391, Dec 14, 2010
Filed:
Dec 14, 2004
Appl. No.:
11/011841
Inventors:
Rosanne H Tinkler - Lexington MA, US
Allen W Hairston - Andover MA, US
Assignee:
BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H04N 5/335
H04N 5/217
H04N 9/64
H01L 27/00
H04N 5/228
US Classification:
348302, 348319, 348241, 348246, 2502081
Abstract:
An imaging system configured with readout circuit redundancy is disclosed. Pixel data from a particular column can be steered around a defective readout circuit to an operational readout circuit. Thus, larger imaging arrays which are generally more prone to common column circuitry defects are enabled. In addition, imaging systems configured with significant on-chip signal processing, which are also more prone to common column circuitry defects, are enabled. The occurrence of lost pixel data from an entire column is eliminated or otherwise reduced, thereby increasing overall operability and yield of the imaging system. The system can be implemented on a single chip or a chip set.

Double Direct Injection Dual Band Sensor Readout Input Circuit

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US Patent:
55235700, Jun 4, 1996
Filed:
Jul 15, 1994
Appl. No.:
8/276037
Inventors:
Allen W. Hairston - Andover MA
Assignee:
Loral Infrared & Imaging Systems, Inc. - Lexington MA
International Classification:
H01L 2700
US Classification:
250349
Abstract:
A double direct injection dual band focal plane array input circuit provides simultaneous and separate integration of the current from two sensors which share a common node. The sensors are constant voltage and variable current sensors such as HgCdTe infrared photodiodes. The sensor voltage biases are independently adjustable. Multiple integration of the signal from one sensor may be performed within one integration time of the other sensor. The circuit is used in staring infrared dual band focal plane arrays and may be used process information from more than two sensors.

Low Power In-Pixel Single Slope Analog To Digital Converter (Adc)

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US Patent:
20210250536, Aug 12, 2021
Filed:
Feb 11, 2020
Appl. No.:
16/787741
Inventors:
- Nashua NH, US
Dimitre P. Dimitrov - Wayland MA, US
Allen W. Hairston - Andover MA, US
Assignee:
BAE SYSTEMS Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H04N 5/378
H03M 1/34
H03M 1/56
H04N 5/376
Abstract:
Techniques, systems, architectures, and methods for reducing peak power during an Analog-to-Digital Conversion (ADC) process, in embodiments on a Focal Plane Array (FPA).

High Voltage Gain Switched Capacitor Filter Integration

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US Patent:
20200193099, Jun 18, 2020
Filed:
Jul 27, 2017
Appl. No.:
16/633223
Inventors:
- Nashua NH, US
Allen W. Hairston - Andover MA, US
Assignee:
BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
G06G 7/184
G06F 7/64
Abstract:
A method of operating switched capacitor filter integration circuits by pre-charging a final filter capacitor thereof with the final full voltage gain value during a first subframe to obtain an enhanced signal to noise ratio without changes to the circuit or components thereof.

Dual Gain Imaging Digital Pixel Memory

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US Patent:
20200177833, Jun 4, 2020
Filed:
Feb 6, 2020
Appl. No.:
16/783492
Inventors:
- Nashua NH, US
Allen W. Hairston - Andover MA, US
Assignee:
BAE SYSTEMS Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H04N 5/378
H01L 27/146
G05F 3/20
G11C 11/417
Abstract:
Techniques and architectures for simultaneous readout and integration of image data from pixels while increasing their sensitivity and reducing required data rates for moving information off of the chip using pixels configured to conduct Analog-to-Digital Conversions (ADCs) of image data, wherein each pixel operates in a rolling Integrate While Read (IWR) mode using SRAM in place of traditional latches for in-pixel storage.
Allen W Hairston from Andover, MA, age ~64 Get Report