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Alfred E Dunlop

from Kattskill Bay, NY
Age ~71

Alfred Dunlop Phones & Addresses

  • 3595 Echo Bay Ln, Kattskill Bay, NY 12844
  • Fort Ann, NY
  • 91 Hunterdon Blvd, New Providence, NJ 07974
  • PO Box 124, Kattskill Bay, NY 12844

Resumes

Resumes

Alfred Dunlop Photo 1

Alfred Dunlop

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Location:
Glens Falls, New York Area
Industry:
Semiconductors
Alfred Dunlop Photo 2

Alfred Dunlop

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Location:
United States

Publications

Us Patents

Signal Distribution Scheme In Field Programmable Gate Array (Fpga) Or Field Programmable System Chip (Fpsc) Including Cycle Stealing Units

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US Patent:
6486705, Nov 26, 2002
Filed:
May 25, 2001
Appl. No.:
09/864276
Inventors:
William B. Andrews - Long Pond PA
Alfred E. Dunlop - Murray Hill NJ
John P. Fishburn - Murray Hill NJ
Harold N. Scholz - Allentown PA
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 1900
US Classification:
326 93, 326 40, 326 46
Abstract:
Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements âstealsâ a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.

Reconfigurable Network Interface Architecture

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US Patent:
6721872, Apr 13, 2004
Filed:
Jan 18, 2000
Appl. No.:
09/484720
Inventors:
Alfred Earl Dunlop - New Providence NJ
Asawaree Kalavade - Edison NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
G06F 15177
US Classification:
712 28, 712 29, 709230, 709221
Abstract:
A network interface architecture includes a processor having an associated program memory, and a programmable logic device coupled to the processor. A connection port of the logic device is adapted to be coupled to a medium of a selected network having a defined network protocol, and the logic device has an associated configuration memory. A data communication path is coupled to the processor and the logic device, and is arranged to connect with a host device for transferring data between the host device and a network to which the logic device is coupled. The processor responds to information identifying a selected network by loading corresponding network protocol data from the configuration memory and the program memory into the logic device and the processor. The host device may include, without limitation, a personal, lap top, desk top or hand-held computer, a network appliance, file server, printer, vending machine, cell phone or the like.

Gated Clock Recovery Circuit

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US Patent:
7010077, Mar 7, 2006
Filed:
Nov 20, 2000
Appl. No.:
09/716977
Inventors:
Alfred Earl Dunlop - New Providence NJ, US
Wilhelm Carl Fischer - Westfield NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03D 3/24
US Classification:
375376, 375373, 375375, 331 2, 331 1 A
Abstract:
A gated clock recovery circuit is disclosed that receives an input data stream and generates a frequency and phase aligned clock output. The gated clock recovery circuit substantially instantaneously adjusts the generated clock signal to phase changes in the incoming data stream. In addition, the gated clock recovery circuit generates the clock output signal using only transmitted non-predetermined data. The gated clock recovery circuit includes two PLL circuits. The first PLL (PLL) adjusts to the frequency of the transmitter, and provides a bias voltage, CAP, to the second PLL (PLL) to indirectly initially tune the second PLL. The bias voltage, CAP, is applied to the second PLL through a transmission gate (or switch) that is initially in a closed (short) position. Thus, the first PLL drives the bias voltage, CAP, of the second PLL, to align the frequency with the transmitter, until received data opens the transmission gate. Thereafter, the bias voltage, CAP, is removed and the second PLL can operate without being controlled by PLL so that the second PLL oscillates in phase with the received data.

Reconfigurable Fabric For Socs Using Functional I/O Leads

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US Patent:
7058918, Jun 6, 2006
Filed:
Apr 28, 2003
Appl. No.:
10/425101
Inventors:
Miron Abramovici - Berkeley Heights NJ, US
Alfred E. Dunlop - Kattskill Bay NY, US
Assignee:
Dafca, Inc. - Framingham MA
International Classification:
G06F 17/50
US Classification:
716 12, 716 17, 716 18
Abstract:
An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.

Clock, Data And Time Recovery Using Bit-Resolved Timing Registers

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US Patent:
7123675, Oct 17, 2006
Filed:
Sep 25, 2002
Appl. No.:
10/255008
Inventors:
Glenn M Boles - Fords NJ, US
Alfred Earl Dunlop - Kattskill Bay NY, US
Ilija Hadzic - Millington NJ, US
Manyalibo Joseph Matthews - Jersey City NJ, US
Dusan Suvakovic - Florham Park NJ, US
Doutje T. Van Veen - Berkeley Heights NJ, US
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H04L 7/00
US Classification:
375354, 327141, 370503, 709248, 714 12
Abstract:
A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.

Method And Apparatus For Multiphase, Fast-Locking Clock And Data Recovery

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US Patent:
7242739, Jul 10, 2007
Filed:
Jun 12, 2003
Appl. No.:
10/460572
Inventors:
Glenn M Boles - Fords NJ, US
Alfred Earl Dunlop - Kattskill Bay NY, US
Manyalibo Joseph Matthews - Jersey City NJ, US
Dusan Suvakovic - Florham Park NJ, US
Doutje T. Van Veen - Berkeley Heights NJ, US
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H03D 3/24
US Classification:
375375, 375376, 375371
Abstract:
A method and apparatus for clock and data recovery that is advantageous in burst-mode systems is disclosed. This clock and data recovery method allows a) fast locking to a rapidly changed phase of the transmission clock, and b) stable tracking of a slowly changing phase of the transmission clock. Such fast locking minimizes the “guard band” between consecutive transmission bursts, while stable tracking provides reliable data tracking, resulting in the efficient use of bandwidth. A plurality of clock signals, is generated, each having a different phase. The phase of an input signal data stream is determined and a desired clock signal in the plurality that corresponds to the phase of the input data stream is selected and used to sample the input signal data stream.

Transistor Sizing System For Integrated Circuits

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US Patent:
48274283, May 2, 1989
Filed:
Nov 15, 1985
Appl. No.:
6/798557
Inventors:
Alfred E. Dunlop - New Providence NJ
John P. Fishburn - North Plainfield NJ
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ
International Classification:
G06F 1560
US Classification:
364491
Abstract:
A method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met. The design improvement is realized by selecting a model for the delay through each active element of the circuit that is characterized by a convex-function of the logarithm of the active element's size. Using the convex function model, with each iteration a static timing analysis of the circuit identifies the output that most grievously violates the specified constraint. With that output selected, an analysis of the path's timing structure identifies the active element in that path whose change in size would yield the largest improvement in performance. The size of that active element is adjusted accordingly and the iteration is repeated. For further improvement, the interconnection pattern of subnetworks of the circuit is evaluated and rearranged to improve performance.

Method And Apparatus For Clock Recovery

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US Patent:
52372901, Aug 17, 1993
Filed:
May 8, 1992
Appl. No.:
7/880428
Inventors:
Mihai Banu - Murray Hill NJ
Alfred E. Dunlop - Murray Hill NJ
Assignee:
AT&T Bell Laboratories - Murray Hill NJ
International Classification:
H03L 706
H04L 7033
US Classification:
331 2
Abstract:
A method and apparatus for recovering the phase of a signal which may change at periodic intervals is disclosed which comprises gated variable frequency oscillators. These results are obtained in an illustrative embodiment of the present invention in which an incoming signal is fed into a gated oscillator and the complement of the incoming signal is fed into a matching gated oscillator. Advantageously, the respective outputs of the two oscillators are fed into a Boolean NOR gate. When the gated oscillators are designed to oscillate at the frequency of the incoming signal, the output waveform will have a bounded phase relationship with respect to the incoming signal.

Wikipedia

Alfred Dunlop

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Alfred Dunlop (12 January 1875 7 April 1933) was an Australian tennis player, born in Christchurch, New Zealand. He won the doubles title at the ...

Alfred E Dunlop from Kattskill Bay, NY, age ~71 Get Report