Inventors:
Alfred Earl Dunlop - New Providence NJ, US
Wilhelm Carl Fischer - Westfield NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03D 3/24
US Classification:
375376, 375373, 375375, 331 2, 331 1 A
Abstract:
A gated clock recovery circuit is disclosed that receives an input data stream and generates a frequency and phase aligned clock output. The gated clock recovery circuit substantially instantaneously adjusts the generated clock signal to phase changes in the incoming data stream. In addition, the gated clock recovery circuit generates the clock output signal using only transmitted non-predetermined data. The gated clock recovery circuit includes two PLL circuits. The first PLL (PLL) adjusts to the frequency of the transmitter, and provides a bias voltage, CAP, to the second PLL (PLL) to indirectly initially tune the second PLL. The bias voltage, CAP, is applied to the second PLL through a transmission gate (or switch) that is initially in a closed (short) position. Thus, the first PLL drives the bias voltage, CAP, of the second PLL, to align the frequency with the transmitter, until received data opens the transmission gate. Thereafter, the bias voltage, CAP, is removed and the second PLL can operate without being controlled by PLL so that the second PLL oscillates in phase with the received data.