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Alexander Rabinovitch

from Shrewsbury, MA
Age ~51
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Also known as:
Alexander Rabinovich, Alexande Rabinovitch
Phone and address:
4 Shannon Dr, Shrewsbury, MA 01545
(508) 791-6982
Related to:
Joseph Rabinovitch, 30Marina Rabinovitch, 52Avital Rabinovitch, 26
Connected to:
Abraham Rabinovich, 90Adam J Rabinovitz, 42Adi Rabinovich, 50Alicia N Rabinowitz, 60Alison L Rabinovitz, 55Andrea J Rabinowitz, 58Anna Rabinowitz, 91Ariana R Rabinovitch, 49Asher D Rabinowitz, 74Barry Rabinovitch, 70

Alexander Rabinovitch Phones & Addresses

  • 4 Shannon Dr, Shrewsbury, MA 01545 (508) 791-6982
  • 111 Broadmeadow St, Marlborough, MA 01752 (508) 481-9356
  • Coram, NY

Work

Position: Homemaker

Education

Degree: High school graduate or higher

Emails

a***[email protected]

Publications

Us Patents

Logic Simulation And/Or Emulation Which Follows Hardware Semantics

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US Patent:
20100280814, Nov 4, 2010
Filed:
Apr 29, 2009
Appl. No.:
12/432017
Inventors:
Alexander Rabinovitch - Shrewsbury MA, US
Ramesh Narayanaswamy - Palo Alto CA, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
703 16
Abstract:
Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.

Compact Circuit-Simulation Output

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US Patent:
20090254331, Oct 8, 2009
Filed:
Apr 2, 2008
Appl. No.:
12/060984
Inventors:
Alexander Rabinovitch - Shrewsbury MA, US
Manish Shroff - Marlborough MA, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
703 15
Abstract:
Embodiments of a computer system for simulating a circuit are described. During a first mode of the simulation, the computer system stores primary signals and circuit relationships between primary signals and secondary signals associated with a portion of the circuit in a file, where the primary signals are independent of gate outputs in the portion of the circuit, and the secondary signals are driven by gates in the portion of the circuit. Moreover, during a second mode of the simulation, the computer system stores dynamic changes in additional relationships between signals to the file, where the signals can include primary signals, secondary signals, or both.

Partitioning And Routing Multi-Slr Fpga For Emulation And Prototyping

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US Patent:
20170364621, Dec 21, 2017
Filed:
Jun 16, 2016
Appl. No.:
15/184266
Inventors:
- Mountain View CA, US
Alexander RABINOVITCH - Shrewsbury MA, US
International Classification:
G06F 17/50
Abstract:
A computer-implemented method for configuring a hardware verification system includes receiving, in the computer, a first data representative of a first design. The method further includes performing a first mapping of the first data to generate a second data in accordance with a first cost function and one or more first delays each associated with a different one of a first multitude of paths. One of the first multitude of paths includes a critical path characterized by a second delay. The method further includes performing a second mapping of the second data to generate a third data in accordance with a second cost function and a multitude of third delays each associated with a different one of a second multitude of paths and the second delay. The method further includes compiling the third data for configuring the hardware verification system.

Deterministic Identifiers For Source Code Elements

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US Patent:
20170124305, May 4, 2017
Filed:
Oct 30, 2015
Appl. No.:
14/929112
Inventors:
- Mountain View CA, US
Alexander Rabinovitch - Shrewsbury MA, US
International Classification:
G06F 21/14
G06F 21/60
Abstract:
Multiple computer systems each include at least one EDA tool that performs certain EDA functions. Each computer system also includes source code of a design with the names of source code elements and an encoding module that generates unique identifiers for the source code elements according to a specific encoding algorithm. The encoding module identifies each source code element included in the source code. For each source code element, the encoding module generates a unique identifier by applying the encoding algorithm to the name of the element. When electronic design information is going to be transmitted to another computer system and the electronic design information includes source code elements, the encoding module encodes the information by replacing each source code element with the unique identifier generated for the element.

Overlaying Of Clock And Data Propagation In Emulation

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US Patent:
20170109466, Apr 20, 2017
Filed:
Mar 29, 2016
Appl. No.:
15/083807
Inventors:
- Mountain View CA, US
Alexander Rabinovitch - Shrewsbury MA, US
International Classification:
G06F 17/50
Abstract:
A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving, in the computer, a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system. The method further includes transforming, using the computer, the first data into a second data representative of a second design. The second data includes a third data associated with a second sequential element including functionality of the first sequential element and a fourth data associated with a first logic circuit. The evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i−1 of the hardware verification system when the second data is compiled for programming into the hardware verification system, where i is an integer number.

Efficient Waveform Generation For Emulation

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US Patent:
20160328499, Nov 10, 2016
Filed:
Jan 26, 2016
Appl. No.:
15/007040
Inventors:
- Mountain View CA, US
Alexander Rabinovitch - Shrewsbury MA, US
International Classification:
G06F 17/50
Abstract:
An emulation environment includes a host system and an emulator. The host system configures the emulator to emulate a design under test (DUT) and the emulator emulates the DUT accordingly. During emulation, the emulator traces limited signals of the DUT and stores values of the traced signals. When values of certain signals of the DUT are needed for analysis or verification of the DUT but the signals were not traced by the emulator, the host system simulates one or more sections of the DUT to obtain values of the signals. Signals traced by the emulator are used as inputs to simulate the one or more sections.
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Alexander Rabinovitch from Shrewsbury, MA, age ~51 Get Report