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Alan J Greenberger

from Allentown, PA
Age ~78
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Also known as:
Alan Joel Greenberger
Phone and address:
1133 33Rd St, Allentown, PA 18104
(610) 398-2445
Related to:
Kristin Washburn Spang, 46Christine F Spang, 75
Connected to:
Abby J Greenberg, 89Adina Greenberg, 68Alfred G Greenberg, 100Alla Greenberg, 42Alyson Greenberg, 34Alyssa R Greenberg, 50Arielle Greenberg, 35Berton Greenberg, 84Billy Greenberg, 80Brant Greenberg, 62

Alan Greenberger Phones & Addresses

  • 1133 33Rd St, Allentown, PA 18104 (610) 398-2445
  • 1127 33Rd St, Allentown, PA 18104
  • Berkeley Heights, NJ
  • Old Zionsville, PA
  • Scotch Plains, NJ
  • 1133 N 33Rd St, Allentown, PA 18104

Work

Position: Consultant

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Brandeis University 1967 to 1973 Specialities: Physics

Emails

a***[email protected]

Industries

Legal Services

Resumes

Resumes

Alan Greenberger Photo 1

Consultant

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Location:
Allentown, PA
Industry:
Legal Services
Work:

Consultant
Technology Patents & Licensing Dec 2007 - Mar 2009
Senior Patent Analyst
Lsi Corporation Feb 1981 - Jan 2006
Distinguished Member Technical Staff
Princeton Plasma Physics Laboratory (Pppl) Feb 1973 - Jan 1981
Senior Technical Staff
Education:
Brandeis University 1967 - 1973
Doctorates, Doctor of Philosophy, Physics University of Rochester 1963 - 1967
Bachelors, Bachelor of Science, Physics Rensselaer Polytechnic Institute
Bachelor of Architecture, Bachelors

Business Records

Name / Title
Company / Classification
Phones & Addresses
Alan Greenberger
Principal
City of Philadelphia
Municipality Office · Executive Office · General Government · Municipality · Land/Mineral/Wildlife Conservation · Public Finance/Taxation/Monetary Policy · Administrative Social/Manpower Programs · Business Association Executive Office
(215) 683-4400, (215) 683-6050, (215) 683-2058, (215) 683-4347

Publications

Us Patents

Complex Number Multiplier Circuit

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US Patent:
6411979, Jun 25, 2002
Filed:
Jun 14, 1999
Appl. No.:
09/333071
Inventors:
Alan Joel Greenberger - Allentown PA
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
G06F 752
US Classification:
708622
Abstract:
A digital circuit for computing a function consisting of sums and differences of the products of a first vector of N multipliers and a second vector of M multiplicands, where at least one of N and M is greater than one include N multibit recoding circuits and M multiples generator circuits. Each recoding circuit receives a respective multiplier as input and produces a radix-2 signed digit representation of the multiplier as output. Each multiples generator receives a respective multiplicand as input and producing multiples of the multiplicand between one and 2 as output. The output of N recoding circuits and M multiples generator circuits are fed to an NÃM array of partial product summers. Each partial product summer produces a respective product output, the set of outputs of the partial product summers comprising the product of each of the multipliers with each of the multiplicands. At least one adder receives the product outputs of the partial product summers and produces a summed output corresponding to the function being computed.

Controller Apparatus And Method For Improved Data Transfer

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US Patent:
7284082, Oct 16, 2007
Filed:
Aug 19, 2004
Appl. No.:
10/921723
Inventors:
Alan J. Greenberger - Allentown PA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 13/36
US Classification:
710312, 710316
Abstract:
Embodiments of the invention include a controller apparatus, system and method for transferring data between data storage devices within a computer system. The inventive controller apparatus includes device interface logic for connecting the controller to a plurality of data storage devices, e. g. , a hard disk device and a CD-RW device, and host interface logic for connecting the controller to a host or host computer via a bus such as a PCI bus. The host includes a number of other components, e. g. , a host memory, connected thereto. The controller includes switching circuitry that allows data to be transferred directly from the source data storage device to at least one destination data storage device, i. e. , without the transferred data passing from the controller through the bus to the host and/or the host memory. The switching circuitry includes the appropriate buffering circuitry and multiplexing circuitry to transfer data directly from the source device to the destination device in a manner that relieves the host, the host memory, and the bus between the host and the controller of much of the data transfer responsibilities during most data transfer operations.

Digital Real Time Music Synthesizer

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US Patent:
41777069, Dec 11, 1979
Filed:
Jul 7, 1978
Appl. No.:
5/922803
Inventors:
Alan J. Greenberger - Hopewell NJ
International Classification:
G10H 106
G10H 510
US Classification:
84 101
Abstract:
This disclosure pertains to a digitalized music synthesizer functioning in the real time domain to continuously update, in an asynchronous manner, a continuing approximation of a desired waveform by utilizing its memory of the recent history of the operation of the keyboard of the apparatus. A real time clock and a microcomputer are both driven by a single crystal oscillator, operating at any arbitrary frequency that need not correspond with the frequency of the fundamental or harmonic waves to be produced by the apparatus. A memory of the recent history of keyboard events is maintained. The microcomputer utilizes an algorithm employing square waves as a basis and a differential correcting technique which minimizes the quantity of square wave defining terms that need be computed by only recomputing at each time, corrections to the previous computation. The digitalized output, represented by summing the transient amplitudes comprising the updated approximation to the desired waveform, is fed into a digital to analog converter, an amplifier and a speaker system.

Content Addressable Semiconductor Memory Arrays

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US Patent:
47945591, Dec 27, 1988
Filed:
Jul 5, 1984
Appl. No.:
6/628165
Inventors:
Alan J. Greenberger - Berkeley Heights NJ
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ
International Classification:
G11C 1504
G11C 1124
US Classification:
365 49
Abstract:
A semiconductor memory circuit is arranged with an ordinary crosspoint row-column array of dynamic capacitor memory storage cells. Word serial content addressing is enabled by adding a separate combinational logic device, only one such device for each entire column bit line, typically comprising a comparator feeding a NAND gate to which masking data can be supplied.
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Alan J Greenberger from Allentown, PA, age ~78 Get Report