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Akilesh Parameswar

from San Jose, CA
Age ~56
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Also known as:
Aklesh Parameswar, Yukiko Parameswar, Akil Parameswar, Auiles Parameswar, Parameswar Akilesh, H Parameswar
Phone and address:
3638 Julio Ave, San Jose, CA 95124
(408) 266-8001
Related to:
Erin M Rajski, 58Kathleen Ostroff, 77Grace Toups, 45Kevin Fennell, 54Tania Benoit, 52
Connected to:
Aravind Parameswaran, 37Ashok G Parameswaran, 54Dan S Paramesh, 70Kavitha Parameswaran, 54Madhu Parameswaran, 45Narayan Parameshwar, 54Pramod Parameswaran, 45Senthil K Parameswaran, 55Subhash K Parameswaran, 58Vignesh Parameswaran, 34

Akilesh Parameswar Phones & Addresses

  • 3638 Julio Ave, San Jose, CA 95124 (408) 266-8001
  • 335 Elan Village Ln, San Jose, CA 95134 (408) 577-1120
  • Santa Clara, CA
  • 3638 Julio Ave, San Jose, CA 95124 (408) 425-0996

Work

Company: Cadence design systems 2013 to 2013 Position: Senior principal design engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: University of Zimbabwe 1985 to 1988 Specialities: Electrical Engineering

Skills

Soc • Processors • Asic • Verilog • Eda • Microprocessors • Embedded Systems • Systemverilog • Functional Verification • Computer Architecture • Digital Signal Processors • Vlsi • Ic • Rtl Design • Software Engineering

Emails

a***[email protected]

Industries

Semiconductors

Resumes

Resumes

Akilesh Parameswar Photo 1

Akilesh Parameswar

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Cadence Design Systems 2013 - 2013
Senior Principal Design Engineer
Tensilica 2013 - 2013
Mts
Taec 1994 - 1998
Senior Staff Engineer
Toshiba Americas 1991 - 1994
Research Engineer
Cf Tulley and Associates 1986 - 1986
Intern
Education:
University of Zimbabwe 1985 - 1988
Bachelors, Bachelor of Science, Electrical Engineering International School of Lusaka
Skills:
Soc
Processors
Asic
Verilog
Eda
Microprocessors
Embedded Systems
Systemverilog
Functional Verification
Computer Architecture
Digital Signal Processors
Vlsi
Ic
Rtl Design
Software Engineering

Publications

Us Patents

Automated Processor Generation System And Method For Designing A Configurable Processor

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US Patent:
7437700, Oct 14, 2008
Filed:
Nov 16, 2005
Appl. No.:
11/281217
Inventors:
Albert Ren-Rui Wang - Fremont CA, US
Richard Ruddell - Los Gatos CA, US
David William Goodwin - Sunnyvale CA, US
Earl A. Killian - Los Altos Hills CA, US
Nupur Bhattacharyya - Mountain View CA, US
Marines Puig Medina - San Jose CA, US
Walter David Lichtenstein - Belmont MA, US
Pavlos Konas - Mountain View CA, US
Rangarajan Srinivasan - Los Gatos CA, US
Christopher Mark Songer - Mountain View CA, US
Akilesh Parameswar - San Jose CA, US
Dror E. Maydan - Palo Alto CA, US
Ricardo E. Gonzalez - Menlo Park CA, US
Assignee:
Tensilica, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 18, 716 1, 716 17
Abstract:
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

System And Method For Generating A Configurable Processor Supporting A User-Defined Plurality Of Instruction Sizes

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US Patent:
7937559, May 3, 2011
Filed:
Jun 11, 2007
Appl. No.:
11/761322
Inventors:
Akilesh Parameswar - San Jose CA, US
James Alexander Stuart Fiske - Palo Alto CA, US
Ricardo E. Gonzalez - Menlo Park CA, US
Assignee:
Tensilica, Inc. - Santa Clara CA
International Classification:
G06F 9/00
US Classification:
712 37, 712 36
Abstract:
A processor generation system includes the ability to describe processors with three instruction sizes. In one example implementation, instructions can be 16-, 24- and 64-bits. This enables a new range of architectures that can exploit parallelism in architectures. In particular, this enables the generation of VLIW architectures. According to another aspect, the processor generator allows a designer to add a configurable number of load/store units to the processor. In order to accommodate multiple load/store units, local memories connected to the processor can have multiple read and write ports (one for each load/store unit). This further allows the local memories to be connected in any arbitrary connection topology. Connection box hardware is automatically generated that provides an interface between the load/store units and the local memories based on the configuration.

Automated Processor Generation System And Method For Designing A Configurable Processor

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US Patent:
8161432, Apr 17, 2012
Filed:
Oct 9, 2008
Appl. No.:
12/248890
Inventors:
Albert Ren-Rui Wang - Fremont CA, US
Richard Ruddell - Los Gatos CA, US
David William Goodwin - Sunnyvale CA, US
Earl A. Killian - Los Altos CA, US
Nupur Bhattacharyya - Mountain View CA, US
Marines Puig Medina - San Jose CA, US
Walter David Lichtenstein - Belmont MA, US
Pavlos Konas - Mountain View CA, US
Rangarajan Srinivasan - Los Gatos CA, US
Christopher Mark Songer - Mountain View CA, US
Akilesh Parameswar - San Jose CA, US
Dror E. Maydan - Palo Alto CA, US
Ricardo E. Gonzalez - Menlo Park CA, US
Assignee:
Tensilica, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716101, 716113, 716116
Abstract:
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Method For Performing Pattern Decomposition For A Full Chip Design

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US Patent:
20090125866, May 14, 2009
Filed:
Nov 13, 2008
Appl. No.:
12/270498
Inventors:
ALBERT REN-RUI WANG - FREMONT CA, US
RICHARD RUDDELL - LOS GATOS CA, US
DAVID WILLIAM GOODWIN - SUNNYVALE CA, US
EARL A. KILLIAM - LOS ALTOS HILLS CA, US
NUPUR BHATTACHARYYA - MOUNTAIN VIEW CA, US
MARINES PUIG MEDINA - SAN JOSE CA, US
WALTER DAVID LICHTENSTEIN - BELMONT MA, US
PAVLOS KONAS - MOUNTAIN VIEW CA, US
RANGARAJAN SRINIVASAN - LOS GATOS CA, US
CHRISTOPHER MARK SONGER - MOUNTAIN VIEW CA, US
AKILESH PARAMESWAR - SAN JOSE CA, US
DROR E. MAYDAN - PALO ALTO CA, US
RICARDO E. GONZALEZ - MENLO APRK CA, US
International Classification:
G06F 17/50
US Classification:
716 19, 716 21
Abstract:
A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.

Automated Processor Generation System And Method For Designing A Configurable Processor

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US Patent:
20090172630, Jul 2, 2009
Filed:
Oct 9, 2008
Appl. No.:
12/248883
Inventors:
Albert Ren-Rui Wang - Fremont CA, US
Richard Ruddell - Los Gatos CA, US
David William Goodwin - Sunnyvale CA, US
Earl A. Killian - Los Altos Hills CA, US
Nupur Bhattacharyya - Mountain View CA, US
Marines Puig Medina - San Jose CA, US
Walter David Lichtenstein - Belmont MA, US
Pavlos Konas - Mountain View CA, US
Rangarajan Srinivasan - Los Gatos CA, US
Christopher Mark Songer - Mountain View CA, US
Akilesh Parameswar - San Jose CA, US
Dror E. Maydan - Palo Alto CA, US
Ricardo E. Gonzalez - Menlo Park CA, US
International Classification:
G06F 17/50
US Classification:
716 18
Abstract:
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Automated Processor Generation System For Designing A Configurable Processor And Method For The Same

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US Patent:
7036106, Apr 25, 2006
Filed:
Feb 17, 2000
Appl. No.:
09/506502
Inventors:
Albert Ren-Rui Wang - Fremont CA, US
Richard Ruddell - Los Gatos CA, US
David William Goodwin - Sunnyvale CA, US
Earl A. Killian - Los Altos Hills CA, US
Nupur Bhattacharyya - Mountain View CA, US
Marines Puig Medina - San Jose CA, US
Walter David Lichtenstein - Belmont MA, US
Pavlos Konas - Mountain View CA, US
Rangarajan Srinivasan - Los Gatos CA, US
Christopher Mark Songer - Mountain View CA, US
Akilesh Parameswar - San Jose CA, US
Dror E. Maydan - Palo Alto CA, US
Ricardo E. Gonzalez - Menlo Park CA, US
Assignee:
Tensilica, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 18, 716 1, 716 2, 716 17, 703 15
Abstract:
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
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Akilesh Parameswar from San Jose, CA, age ~56 Get Report